cpldfit:  version J.30                              Xilinx Inc.
                                  Fitter Report
Design Name: gc_ide                              Date:  8-26-2010, 11:40AM
Device Used: XC95144XL-5-TQ100
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
92 /144 ( 64%) 451 /720  ( 63%) 230/432 ( 53%)   85 /144 ( 59%) 27 /81  ( 33%)

** Function Block Resources **

Function    Mcells      FB Inps     Pterms      IO          
Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot    
FB1          18/18*      36/54       76/90       4/11
FB2           4/18       22/54       18/90       2/10
FB3          12/18       31/54       58/90       1/10
FB4          10/18       36/54       63/90       1/10
FB5           0/18        0/54        0/90       0/10
FB6          16/18       35/54       87/90       5/10
FB7          18/18*      35/54       84/90       6/10
FB8          14/18       35/54       65/90       5/10
             -----       -----       -----      -----    
             92/144     230/432     451/720     24/81 

* - Resource is exhausted

** Global Control Resources **

Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    3           3    |  I/O              :    23      73
Output        :    8           8    |  GCK/IO           :     2       3
Bidirectional :   16          16    |  GTS/IO           :     2       4
GCK           :    0           0    |  GSR/IO           :     0       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     27          27

** Power Data **

There are 92 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
*************************  Summary of Mapped Logic  ************************

** 24 Outputs **

Signal              Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                Pts   Inps          No.  Type    Use     Mode Rate State
ide_adr<1>          1     2     FB1_5   13   I/O     O       STD  FAST 
ide_adr<0>          1     2     FB1_8   15   I/O     O       STD  FAST 
ide_adr<3>          1     2     FB1_12  18   I/O     O       STD  FAST 
ide_rd              8     13    FB1_17  22   GCK/I/O O       STD  FAST RESET
ide_adr<4>          1     2     FB2_5   1    GTS/I/O O       STD  FAST 
ide_adr<2>          1     2     FB2_8   3    GTS/I/O O       STD  FAST 
ide_wr              4     9     FB3_2   23   GCK/I/O O       STD  FAST RESET
exi_out             27    31    FB4_9   92   I/O     O       STD  FAST RESET
ide_dat<11>         4     11    FB6_2   74   I/O     I/O     STD  FAST RESET
ide_dat<15>         4     11    FB6_6   77   I/O     I/O     STD  FAST RESET
ide_dat<14>         4     11    FB6_8   78   I/O     I/O     STD  FAST RESET
ide_dat<13>         4     11    FB6_11  80   I/O     I/O     STD  FAST RESET
ide_dat<12>         4     11    FB6_14  82   I/O     I/O     STD  FAST RESET
ide_dat<0>          4     11    FB7_5   52   I/O     I/O     STD  FAST RESET
ide_dat<1>          4     11    FB7_8   54   I/O     I/O     STD  FAST RESET
ide_dat<2>          4     11    FB7_11  56   I/O     I/O     STD  FAST RESET
ide_dat<3>          4     11    FB7_12  58   I/O     I/O     STD  FAST RESET
ide_dat<4>          4     11    FB7_14  59   I/O     I/O     STD  FAST RESET
ide_dat<5>          4     11    FB7_17  61   I/O     I/O     STD  FAST RESET
ide_dat<6>          4     11    FB8_5   64   I/O     I/O     STD  FAST RESET
ide_dat<7>          4     11    FB8_8   66   I/O     I/O     STD  FAST RESET
ide_dat<8>          4     11    FB8_9   67   I/O     I/O     STD  FAST RESET
ide_dat<9>          4     11    FB8_12  70   I/O     I/O     STD  FAST RESET
ide_dat<10>         4     11    FB8_15  72   I/O     I/O     STD  FAST RESET

** 68 Buried Nodes **

Signal              Total Total Loc     Pwr  Reg Init
Name                Pts   Inps          Mode State
exi_address<0>      9     14    FB1_1   STD  RESET
rdmult_cnt<9>       4     23    FB1_2   STD  RESET
rdmult_cnt<8>       4     22    FB1_3   STD  RESET
rdmult_cnt<7>       4     21    FB1_4   STD  RESET
rdmult_cnt<6>       4     20    FB1_6   STD  RESET
rdmult_cnt<15>      4     29    FB1_7   STD  RESET
rdmult_cnt<14>      4     28    FB1_9   STD  RESET
rdmult_cnt<13>      4     27    FB1_10  STD  RESET
rdmult_cnt<12>      4     26    FB1_11  STD  RESET
rdmult_cnt<11>      4     25    FB1_13  STD  RESET
rdmult_cnt<10>      4     24    FB1_14  STD  RESET
exi_address<1>      9     14    FB1_15  STD  RESET
do_8bit             4     15    FB1_16  STD  RESET
rdmult              3     28    FB1_18  STD  RESET
$OpTx$FX_DC$142     8     11    FB2_1   STD  
$OpTx$FX_DC$141     8     11    FB2_18  STD  
exi_count<0>        3     11    FB3_8   STD  RESET
do_write            3     12    FB3_9   STD  RESET
exi_count<3>        4     11    FB3_10  STD  RESET
exi_data1<9>        5     13    FB3_11  STD  RESET
exi_data1<8>        5     13    FB3_12  STD  RESET
exi_data1<7>        5     13    FB3_13  STD  RESET
exi_data1<6>        5     13    FB3_14  STD  RESET
exi_data1<5>        5     13    FB3_15  STD  RESET
exi_data1<4>        5     13    FB3_16  STD  RESET
exi_data1<3>        5     13    FB3_17  STD  RESET
exi_address<4>      9     14    FB3_18  STD  RESET
exi_count<7>        3     9     FB4_1   STD  RESET
exi_count<6>        3     8     FB4_2   STD  RESET
exi_count<5>        3     7     FB4_3   STD  RESET
exi_count<4>        3     6     FB4_4   STD  RESET
exi_count<2>        3     4     FB4_5   STD  RESET
exi_count<1>        3     3     FB4_6   STD  RESET
exi_data0<1>        6     15    FB4_7   STD  RESET
exi_data0<0>        6     15    FB4_13  STD  RESET
exi_data0<15>       6     15    FB4_15  STD  RESET
inirdmult           3     13    FB6_1   STD  RESET
do_read             4     13    FB6_3   STD  RESET
exi_data0<9>        6     15    FB6_4   STD  RESET
exi_data0<8>        6     15    FB6_5   STD  RESET

Signal              Total Total Loc     Pwr  Reg Init
Name                Pts   Inps          Mode State
exi_data0<7>        6     15    FB6_7   STD  RESET
exi_data0<6>        6     15    FB6_9   STD  RESET
exi_data0<14>       6     15    FB6_10  STD  RESET
exi_data0<13>       6     15    FB6_12  STD  RESET
exi_data0<12>       6     15    FB6_13  STD  RESET
exi_address<3>      9     14    FB6_15  STD  RESET
exi_address<2>      9     14    FB6_17  STD  RESET
rdmult_cnt<5>       4     19    FB7_1   STD  RESET
rdmult_cnt<4>       4     18    FB7_2   STD  RESET
rdmult_cnt<3>       4     17    FB7_3   STD  RESET
rdmult_cnt<2>       4     16    FB7_4   STD  RESET
rdmult_cnt<1>       4     15    FB7_6   STD  RESET
rdmult_cnt<0>       4     14    FB7_7   STD  RESET
exi_data0<5>        6     15    FB7_9   STD  RESET
exi_data0<4>        6     15    FB7_10  STD  RESET
exi_data0<3>        6     15    FB7_13  STD  RESET
exi_data0<2>        6     15    FB7_15  STD  RESET
exi_data0<11>       6     15    FB7_16  STD  RESET
exi_data0<10>       6     15    FB7_18  STD  RESET
exi_data1<2>        5     13    FB8_6   STD  RESET
exi_data1<1>        5     13    FB8_7   STD  RESET
exi_data1<15>       5     13    FB8_10  STD  RESET
exi_data1<14>       5     13    FB8_11  STD  RESET
exi_data1<13>       5     13    FB8_13  STD  RESET
exi_data1<12>       5     13    FB8_14  STD  RESET
exi_data1<11>       5     13    FB8_16  STD  RESET
exi_data1<10>       5     13    FB8_17  STD  RESET
exi_data1<0>        5     13    FB8_18  STD  RESET

** 3 Inputs **

Signal              Loc     Pin  Pin     Pin     
Name                        No.  Type    Use     
exi_in              FB4_2   87   I/O     I
exi_cs              FB4_6   90   I/O     I
exi_clk             FB6_17  86   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X            - Signal used as input to the macrocell logic.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               36/18
Number of signals used by logic mapping into function block:  36
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
exi_address<0>        9       4<-   0   0     FB1_1         (b)     (b)
rdmult_cnt<9>         4       3<- /\4   0     FB1_2   11    I/O     (b)
rdmult_cnt<8>         4       2<- /\3   0     FB1_3   12    I/O     (b)
rdmult_cnt<7>         4       1<- /\2   0     FB1_4         (b)     (b)
ide_adr<1>            1       0   /\1   3     FB1_5   13    I/O     O
rdmult_cnt<6>         4       0     0   1     FB1_6   14    I/O     (b)
rdmult_cnt<15>        4       0     0   1     FB1_7         (b)     (b)
ide_adr<0>            1       0     0   4     FB1_8   15    I/O     O
rdmult_cnt<14>        4       0     0   1     FB1_9   16    I/O     (b)
rdmult_cnt<13>        4       0     0   1     FB1_10        (b)     (b)
rdmult_cnt<12>        4       0     0   1     FB1_11  17    I/O     (b)
ide_adr<3>            1       0   \/2   2     FB1_12  18    I/O     O
rdmult_cnt<11>        4       2<- \/3   0     FB1_13        (b)     (b)
rdmult_cnt<10>        4       3<- \/4   0     FB1_14  19    I/O     (b)
exi_address<1>        9       4<-   0   0     FB1_15  20    I/O     (b)
do_8bit               4       0   \/1   0     FB1_16        (b)     (b)
ide_rd                8       3<-   0   0     FB1_17  22    GCK/I/O O
rdmult                3       0   /\2   0     FB1_18        (b)     (b)

Signals Used by Logic in Function Block
  1: do_8bit           13: exi_count<5>      25: rdmult_cnt<13> 
  2: do_read           14: exi_count<6>      26: rdmult_cnt<14> 
  3: do_write          15: exi_count<7>      27: rdmult_cnt<15> 
  4: exi_address<0>    16: exi_cs            28: rdmult_cnt<1> 
  5: exi_address<1>    17: exi_in            29: rdmult_cnt<2> 
  6: exi_address<3>    18: ide_rd            30: rdmult_cnt<3> 
  7: exi_clk           19: inirdmult         31: rdmult_cnt<4> 
  8: exi_count<0>      20: rdmult            32: rdmult_cnt<5> 
  9: exi_count<1>      21: rdmult_cnt<0>     33: rdmult_cnt<6> 
 10: exi_count<2>      22: rdmult_cnt<10>    34: rdmult_cnt<7> 
 11: exi_count<3>      23: rdmult_cnt<11>    35: rdmult_cnt<8> 
 12: exi_count<4>      24: rdmult_cnt<12>    36: rdmult_cnt<9> 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
exi_address<0>       ...X..XXXXXXXXXXX.XX.................... 14
rdmult_cnt<9>        .X....XXXXXXXXXXX.X.X......XXXXXXXXX.... 23
rdmult_cnt<8>        .X....XXXXXXXXXXX.X.X......XXXXXXXX..... 22
rdmult_cnt<7>        .X....XXXXXXXXXXX.X.X......XXXXXXX...... 21
ide_adr<1>           ....X..........X........................ 2
rdmult_cnt<6>        .X....XXXXXXXXXXX.X.X......XXXXXX....... 20
rdmult_cnt<15>       .X....XXXXXXXXXXX.X.XXXXXXXXXXXXXXXX.... 29
ide_adr<0>           ...X...........X........................ 2
rdmult_cnt<14>       .X....XXXXXXXXXXX.X.XXXXXX.XXXXXXXXX.... 28
rdmult_cnt<13>       .X....XXXXXXXXXXX.X.XXXXX..XXXXXXXXX.... 27
rdmult_cnt<12>       .X....XXXXXXXXXXX.X.XXXX...XXXXXXXXX.... 26
ide_adr<3>           .....X.........X........................ 2
rdmult_cnt<11>       .X....XXXXXXXXXXX.X.XXX....XXXXXXXXX.... 25
rdmult_cnt<10>       .X....XXXXXXXXXXX.X.XX.....XXXXXXXXX.... 24
exi_address<1>       ...XX.XXXXXXXXXX..XX.................... 14
do_8bit              XXX...XXXXXXXXXXX..X.................... 15
ide_rd               .XX...X..XXXXXXX.XXX.................... 13
rdmult               ......XXXXXXXXXX..XXXXXXXXXXXXXXXXXX.... 28
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               22/32
Number of signals used by logic mapping into function block:  22
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
$OpTx$FX_DC$142       8       3<-   0   0     FB2_1         (b)     (b)
(unused)              0       0   /\3   2     FB2_2   99    GSR/I/O (b)
(unused)              0       0     0   5     FB2_3         (b)     
(unused)              0       0     0   5     FB2_4         (b)     
ide_adr<4>            1       0     0   4     FB2_5   1     GTS/I/O O
(unused)              0       0     0   5     FB2_6   2     GTS/I/O 
(unused)              0       0     0   5     FB2_7         (b)     
ide_adr<2>            1       0     0   4     FB2_8   3     GTS/I/O O
(unused)              0       0     0   5     FB2_9   4     GTS/I/O 
(unused)              0       0     0   5     FB2_10        (b)     
(unused)              0       0     0   5     FB2_11  6     I/O     
(unused)              0       0     0   5     FB2_12  7     I/O     
(unused)              0       0     0   5     FB2_13        (b)     
(unused)              0       0     0   5     FB2_14  8     I/O     
(unused)              0       0     0   5     FB2_15  9     I/O     
(unused)              0       0     0   5     FB2_16        (b)     
(unused)              0       0   \/3   2     FB2_17  10    I/O     (b)
$OpTx$FX_DC$141       8       3<-   0   0     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: exi_address<2>     9: exi_data0<12>     16: exi_data1<11> 
  2: exi_address<4>    10: exi_data0<13>     17: exi_data1<12> 
  3: exi_count<0>      11: exi_data0<14>     18: exi_data1<13> 
  4: exi_count<1>      12: exi_data0<7>      19: exi_data1<14> 
  5: exi_count<2>      13: exi_data0<8>      20: exi_data1<7> 
  6: exi_cs            14: exi_data0<9>      21: exi_data1<8> 
  7: exi_data0<10>     15: exi_data1<10>     22: exi_data1<9> 
  8: exi_data0<11>    

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
$OpTx$FX_DC$142      ..XXX......X..XXXXX.XX.................. 11
ide_adr<4>           .X...X.................................. 2
ide_adr<2>           X....X.................................. 2
$OpTx$FX_DC$141      ..XXX.XXXXX.XX.....X.................... 11
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               31/23
Number of signals used by logic mapping into function block:  31
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   /\4   1     FB3_1         (b)     (b)
ide_wr                4       0     0   1     FB3_2   23    GCK/I/O O
(unused)              0       0     0   5     FB3_3         (b)     
(unused)              0       0     0   5     FB3_4         (b)     
(unused)              0       0     0   5     FB3_5   24    I/O     
(unused)              0       0     0   5     FB3_6   25    I/O     
(unused)              0       0     0   5     FB3_7         (b)     
exi_count<0>          3       0     0   2     FB3_8   27    GCK/I/O (b)
do_write              3       0     0   2     FB3_9   28    I/O     (b)
exi_count<3>          4       0     0   1     FB3_10        (b)     (b)
exi_data1<9>          5       0     0   0     FB3_11  29    I/O     (b)
exi_data1<8>          5       0     0   0     FB3_12  30    I/O     (b)
exi_data1<7>          5       0     0   0     FB3_13        (b)     (b)
exi_data1<6>          5       0     0   0     FB3_14  32    I/O     (b)
exi_data1<5>          5       0     0   0     FB3_15  33    I/O     (b)
exi_data1<4>          5       0     0   0     FB3_16        (b)     (b)
exi_data1<3>          5       0     0   0     FB3_17  34    I/O     (b)
exi_address<4>        9       4<-   0   0     FB3_18        (b)     (b)

Signals Used by Logic in Function Block
  1: ide_dat<5>.PIN    12: exi_clk           22: exi_data1<3> 
  2: ide_dat<4>.PIN    13: exi_count<0>      23: exi_data1<4> 
  3: ide_dat<3>.PIN    14: exi_count<1>      24: exi_data1<5> 
  4: ide_dat<9>.PIN    15: exi_count<2>      25: exi_data1<6> 
  5: ide_dat<8>.PIN    16: exi_count<3>      26: exi_data1<7> 
  6: ide_dat<7>.PIN    17: exi_count<4>      27: exi_data1<8> 
  7: ide_dat<6>.PIN    18: exi_count<5>      28: exi_data1<9> 
  8: do_8bit           19: exi_count<6>      29: exi_in 
  9: do_write          20: exi_count<7>      30: inirdmult 
 10: exi_address<3>    21: exi_cs            31: rdmult 
 11: exi_address<4>   

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
ide_wr               ........X..X..XXXXXXX................... 9
exi_count<0>         .......X...XXXXXXXXXX................... 11
do_write             ...........XXXXXXXXXX.......X.X......... 12
exi_count<3>         .......X...XXXXXXXXXX................... 11
exi_data1<9>         ...X....X..X..XXXXXXX......X.XX......... 13
exi_data1<8>         ....X...X..X..XXXXXXX.....X..XX......... 13
exi_data1<7>         .....X..X..X..XXXXXXX....X...XX......... 13
exi_data1<6>         ......X.X..X..XXXXXXX...X....XX......... 13
exi_data1<5>         X.......X..X..XXXXXXX..X.....XX......... 13
exi_data1<4>         .X......X..X..XXXXXXX.X......XX......... 13
exi_data1<3>         ..X.....X..X..XXXXXXXX.......XX......... 13
exi_address<4>       .........XXXXXXXXXXXX........XX......... 14
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               36/18
Number of signals used by logic mapping into function block:  36
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
exi_count<7>          3       0     0   2     FB4_1         (b)     (b)
exi_count<6>          3       0     0   2     FB4_2   87    I/O     I
exi_count<5>          3       0     0   2     FB4_3         (b)     (b)
exi_count<4>          3       0     0   2     FB4_4         (b)     (b)
exi_count<2>          3       0     0   2     FB4_5   89    I/O     (b)
exi_count<1>          3       0   \/2   0     FB4_6   90    I/O     I
exi_data0<1>          6       2<- \/1   0     FB4_7         (b)     (b)
(unused)              0       0   \/5   0     FB4_8   91    I/O     (b)
exi_out              27      22<-   0   0     FB4_9   92    I/O     O
(unused)              0       0   /\5   0     FB4_10        (b)     (b)
(unused)              0       0   /\5   0     FB4_11  93    I/O     (b)
(unused)              0       0   /\5   0     FB4_12  94    I/O     (b)
exi_data0<0>          6       2<- /\1   0     FB4_13        (b)     (b)
(unused)              0       0   /\2   3     FB4_14  95    I/O     (b)
exi_data0<15>         6       1<-   0   0     FB4_15  96    I/O     (b)
(unused)              0       0   /\1   4     FB4_16        (b)     (b)
(unused)              0       0     0   5     FB4_17  97    I/O     
(unused)              0       0     0   5     FB4_18        (b)     

Signals Used by Logic in Function Block
  1: $OpTx$FX_DC$141   13: exi_count<4>      25: exi_data0<6> 
  2: $OpTx$FX_DC$142   14: exi_count<5>      26: exi_data1<0> 
  3: ide_dat<15>.PIN   15: exi_count<6>      27: exi_data1<15> 
  4: ide_dat<1>.PIN    16: exi_count<7>      28: exi_data1<1> 
  5: ide_dat<0>.PIN    17: exi_cs            29: exi_data1<2> 
  6: do_read           18: exi_data0<0>      30: exi_data1<3> 
  7: do_write          19: exi_data0<15>     31: exi_data1<4> 
  8: exi_clk           20: exi_data0<1>      32: exi_data1<5> 
  9: exi_count<0>      21: exi_data0<2>      33: exi_data1<6> 
 10: exi_count<1>      22: exi_data0<3>      34: exi_in 
 11: exi_count<2>      23: exi_data0<4>      35: exi_out 
 12: exi_count<3>      24: exi_data0<5>      36: inirdmult 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
exi_count<7>         .......XXXXXXXX.X....................... 9
exi_count<6>         .......XXXXXXX..X....................... 8
exi_count<5>         .......XXXXXX...X....................... 7
exi_count<4>         .......XXXXX....X....................... 6
exi_count<2>         .......XXX......X....................... 4
exi_count<1>         .......XX.......X....................... 3
exi_data0<1>         ...X.X.XXXXXXXXXX..X.............X.X.... 15
exi_out              XX...XXXXXXXXXXXXXXXXXXXXXXXXXXXX.X..... 31
exi_data0<0>         ....XX.XXXXXXXXXXX...............X.X.... 15
exi_data0<15>        ..X..X.XXXXXXXXXX.X..............X.X.... 15
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB5  ***********************************
Number of function block inputs used/remaining:               0/54
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB5_1         (b)     
(unused)              0       0     0   5     FB5_2   35    I/O     
(unused)              0       0     0   5     FB5_3         (b)     
(unused)              0       0     0   5     FB5_4         (b)     
(unused)              0       0     0   5     FB5_5   36    I/O     
(unused)              0       0     0   5     FB5_6   37    I/O     
(unused)              0       0     0   5     FB5_7         (b)     
(unused)              0       0     0   5     FB5_8   39    I/O     
(unused)              0       0     0   5     FB5_9   40    I/O     
(unused)              0       0     0   5     FB5_10        (b)     
(unused)              0       0     0   5     FB5_11  41    I/O     
(unused)              0       0     0   5     FB5_12  42    I/O     
(unused)              0       0     0   5     FB5_13        (b)     
(unused)              0       0     0   5     FB5_14  43    I/O     
(unused)              0       0     0   5     FB5_15  46    I/O     
(unused)              0       0     0   5     FB5_16        (b)     
(unused)              0       0     0   5     FB5_17  49    I/O     
(unused)              0       0     0   5     FB5_18        (b)     
*********************************** FB6  ***********************************
Number of function block inputs used/remaining:               35/19
Number of signals used by logic mapping into function block:  35
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
inirdmult             3       0     0   2     FB6_1         (b)     (b)
ide_dat<11>           4       0   \/1   0     FB6_2   74    I/O     I/O
do_read               4       1<- \/2   0     FB6_3         (b)     (b)
exi_data0<9>          6       2<- \/1   0     FB6_4         (b)     (b)
exi_data0<8>          6       1<-   0   0     FB6_5   76    I/O     (b)
ide_dat<15>           4       0   \/1   0     FB6_6   77    I/O     I/O
exi_data0<7>          6       1<-   0   0     FB6_7         (b)     (b)
ide_dat<14>           4       0   \/1   0     FB6_8   78    I/O     I/O
exi_data0<6>          6       1<-   0   0     FB6_9   79    I/O     (b)
exi_data0<14>         6       1<-   0   0     FB6_10        (b)     (b)
ide_dat<13>           4       0   /\1   0     FB6_11  80    I/O     I/O
exi_data0<13>         6       1<-   0   0     FB6_12  81    I/O     (b)
exi_data0<12>         6       2<- /\1   0     FB6_13        (b)     (b)
ide_dat<12>           4       1<- /\2   0     FB6_14  82    I/O     I/O
exi_address<3>        9       5<- /\1   0     FB6_15  85    I/O     (b)
(unused)              0       0   /\5   0     FB6_16        (b)     (b)
exi_address<2>        9       4<-   0   0     FB6_17  86    I/O     I
(unused)              0       0   /\4   1     FB6_18        (b)     (b)

Signals Used by Logic in Function Block
  1: ide_dat<14>.PIN   13: exi_clk           25: exi_data0<13> 
  2: ide_dat<13>.PIN   14: exi_count<0>      26: exi_data0<14> 
  3: ide_dat<12>.PIN   15: exi_count<1>      27: exi_data0<15> 
  4: ide_dat<9>.PIN    16: exi_count<2>      28: exi_data0<6> 
  5: ide_dat<8>.PIN    17: exi_count<3>      29: exi_data0<7> 
  6: ide_dat<7>.PIN    18: exi_count<4>      30: exi_data0<8> 
  7: ide_dat<6>.PIN    19: exi_count<5>      31: exi_data0<9> 
  8: do_read           20: exi_count<6>      32: exi_in 
  9: do_write          21: exi_count<7>      33: ide_wr 
 10: exi_address<1>    22: exi_cs            34: inirdmult 
 11: exi_address<2>    23: exi_data0<11>     35: rdmult 
 12: exi_address<3>    24: exi_data0<12>    

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
inirdmult            .......X....XXXXXXXXXX.........X..X..... 13
ide_dat<11>          ........X...X..XXXXXXXX.........X....... 11
do_read              .......X....XXXXXXXXXX.........X..X..... 13
exi_data0<9>         ...X...X....XXXXXXXXXX........XX.X...... 15
exi_data0<8>         ....X..X....XXXXXXXXXX.......X.X.X...... 15
ide_dat<15>          ........X...X..XXXXXXX....X.....X....... 11
exi_data0<7>         .....X.X....XXXXXXXXXX......X..X.X...... 15
ide_dat<14>          ........X...X..XXXXXXX...X......X....... 11
exi_data0<6>         ......XX....XXXXXXXXXX.....X...X.X...... 15
exi_data0<14>        X......X....XXXXXXXXXX...X.....X.X...... 15
ide_dat<13>          ........X...X..XXXXXXX..X.......X....... 11
exi_data0<13>        .X.....X....XXXXXXXXXX..X......X.X...... 15
exi_data0<12>        ..X....X....XXXXXXXXXX.X.......X.X...... 15
ide_dat<12>          ........X...X..XXXXXXX.X........X....... 11
exi_address<3>       ..........XXXXXXXXXXXX...........XX..... 14
exi_address<2>       .........XX.XXXXXXXXXX...........XX..... 14
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB7  ***********************************
Number of function block inputs used/remaining:               35/19
Number of signals used by logic mapping into function block:  35
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
rdmult_cnt<5>         4       0   /\1   0     FB7_1         (b)     (b)
rdmult_cnt<4>         4       0     0   1     FB7_2   50    I/O     (b)
rdmult_cnt<3>         4       0     0   1     FB7_3         (b)     (b)
rdmult_cnt<2>         4       0     0   1     FB7_4         (b)     (b)
ide_dat<0>            4       0     0   1     FB7_5   52    I/O     I/O
rdmult_cnt<1>         4       0     0   1     FB7_6   53    I/O     (b)
rdmult_cnt<0>         4       0     0   1     FB7_7         (b)     (b)
ide_dat<1>            4       0   \/1   0     FB7_8   54    I/O     I/O
exi_data0<5>          6       1<-   0   0     FB7_9   55    I/O     (b)
exi_data0<4>          6       1<-   0   0     FB7_10        (b)     (b)
ide_dat<2>            4       0   /\1   0     FB7_11  56    I/O     I/O
ide_dat<3>            4       0   \/1   0     FB7_12  58    I/O     I/O
exi_data0<3>          6       1<-   0   0     FB7_13        (b)     (b)
ide_dat<4>            4       0   \/1   0     FB7_14  59    I/O     I/O
exi_data0<2>          6       1<-   0   0     FB7_15  60    I/O     (b)
exi_data0<11>         6       1<-   0   0     FB7_16        (b)     (b)
ide_dat<5>            4       0   /\1   0     FB7_17  61    I/O     I/O
exi_data0<10>         6       1<-   0   0     FB7_18        (b)     (b)

Signals Used by Logic in Function Block
  1: ide_dat<5>.PIN    13: exi_count<3>      25: exi_data0<4> 
  2: ide_dat<4>.PIN    14: exi_count<4>      26: exi_data0<5> 
  3: ide_dat<3>.PIN    15: exi_count<5>      27: exi_in 
  4: ide_dat<2>.PIN    16: exi_count<6>      28: ide_wr 
  5: ide_dat<11>.PIN   17: exi_count<7>      29: inirdmult 
  6: ide_dat<10>.PIN   18: exi_cs            30: rdmult_cnt<0> 
  7: do_read           19: exi_data0<0>      31: rdmult_cnt<1> 
  8: do_write          20: exi_data0<10>     32: rdmult_cnt<2> 
  9: exi_clk           21: exi_data0<11>     33: rdmult_cnt<3> 
 10: exi_count<0>      22: exi_data0<1>      34: rdmult_cnt<4> 
 11: exi_count<1>      23: exi_data0<2>      35: rdmult_cnt<5> 
 12: exi_count<2>      24: exi_data0<3>     

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
rdmult_cnt<5>        ......X.XXXXXXXXXX........X.XXXXXXX..... 19
rdmult_cnt<4>        ......X.XXXXXXXXXX........X.XXXXXX...... 18
rdmult_cnt<3>        ......X.XXXXXXXXXX........X.XXXXX....... 17
rdmult_cnt<2>        ......X.XXXXXXXXXX........X.XXXX........ 16
ide_dat<0>           .......XX..XXXXXXXX........X............ 11
rdmult_cnt<1>        ......X.XXXXXXXXXX........X.XXX......... 15
rdmult_cnt<0>        ......X.XXXXXXXXXX........X.XX.......... 14
ide_dat<1>           .......XX..XXXXXXX...X.....X............ 11
exi_data0<5>         X.....X.XXXXXXXXXX.......XX.X........... 15
exi_data0<4>         .X....X.XXXXXXXXXX......X.X.X........... 15
ide_dat<2>           .......XX..XXXXXXX....X....X............ 11
ide_dat<3>           .......XX..XXXXXXX.....X...X............ 11
exi_data0<3>         ..X...X.XXXXXXXXXX.....X..X.X........... 15
ide_dat<4>           .......XX..XXXXXXX......X..X............ 11
exi_data0<2>         ...X..X.XXXXXXXXXX....X...X.X........... 15
exi_data0<11>        ....X.X.XXXXXXXXXX..X.....X.X........... 15
ide_dat<5>           .......XX..XXXXXXX.......X.X............ 11
exi_data0<10>        .....XX.XXXXXXXXXX.X......X.X........... 15
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB8  ***********************************
Number of function block inputs used/remaining:               35/19
Number of signals used by logic mapping into function block:  35
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB8_1         (b)     
(unused)              0       0     0   5     FB8_2   63    I/O     
(unused)              0       0     0   5     FB8_3         (b)     
(unused)              0       0     0   5     FB8_4         (b)     
ide_dat<6>            4       0     0   1     FB8_5   64    I/O     I/O
exi_data1<2>          5       0     0   0     FB8_6   65    I/O     (b)
exi_data1<1>          5       0     0   0     FB8_7         (b)     (b)
ide_dat<7>            4       0     0   1     FB8_8   66    I/O     I/O
ide_dat<8>            4       0     0   1     FB8_9   67    I/O     I/O
exi_data1<15>         5       0     0   0     FB8_10        (b)     (b)
exi_data1<14>         5       0     0   0     FB8_11  68    I/O     (b)
ide_dat<9>            4       0     0   1     FB8_12  70    I/O     I/O
exi_data1<13>         5       0     0   0     FB8_13        (b)     (b)
exi_data1<12>         5       0     0   0     FB8_14  71    I/O     (b)
ide_dat<10>           4       0     0   1     FB8_15  72    I/O     I/O
exi_data1<11>         5       0     0   0     FB8_16        (b)     (b)
exi_data1<10>         5       0     0   0     FB8_17  73    I/O     (b)
exi_data1<0>          5       0     0   0     FB8_18        (b)     (b)

Signals Used by Logic in Function Block
  1: ide_dat<15>.PIN   13: exi_count<3>      25: exi_data1<10> 
  2: ide_dat<14>.PIN   14: exi_count<4>      26: exi_data1<11> 
  3: ide_dat<2>.PIN    15: exi_count<5>      27: exi_data1<12> 
  4: ide_dat<1>.PIN    16: exi_count<6>      28: exi_data1<13> 
  5: ide_dat<0>.PIN    17: exi_count<7>      29: exi_data1<14> 
  6: ide_dat<13>.PIN   18: exi_cs            30: exi_data1<15> 
  7: ide_dat<12>.PIN   19: exi_data0<10>     31: exi_data1<1> 
  8: ide_dat<11>.PIN   20: exi_data0<6>      32: exi_data1<2> 
  9: ide_dat<10>.PIN   21: exi_data0<7>      33: ide_wr 
 10: do_write          22: exi_data0<8>      34: inirdmult 
 11: exi_clk           23: exi_data0<9>      35: rdmult 
 12: exi_count<2>      24: exi_data1<0>     

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
ide_dat<6>           .........XXXXXXXXX.X............X....... 11
exi_data1<2>         ..X......XXXXXXXXX.............X.XX..... 13
exi_data1<1>         ...X.....XXXXXXXXX............X..XX..... 13
ide_dat<7>           .........XXXXXXXXX..X...........X....... 11
ide_dat<8>           .........XXXXXXXXX...X..........X....... 11
exi_data1<15>        X........XXXXXXXXX...........X...XX..... 13
exi_data1<14>        .X.......XXXXXXXXX..........X....XX..... 13
ide_dat<9>           .........XXXXXXXXX....X.........X....... 11
exi_data1<13>        .....X...XXXXXXXXX.........X.....XX..... 13
exi_data1<12>        ......X..XXXXXXXXX........X......XX..... 13
ide_dat<10>          .........XXXXXXXXXX.............X....... 11
exi_data1<11>        .......X.XXXXXXXXX.......X.......XX..... 13
exi_data1<10>        ........XXXXXXXXXX......X........XX..... 13
exi_data1<0>         ....X....XXXXXXXXX.....X.........XX..... 13
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********


$OpTx$FX_DC$141 <= ((EXP11_.EXP)
	OR (exi_count(2) AND exi_count(1) AND exi_count(0) AND 
	exi_data0(14))
	OR (exi_count(2) AND exi_count(1) AND NOT exi_count(0) AND 
	exi_data0(13))
	OR (exi_count(2) AND NOT exi_count(1) AND exi_count(0) AND 
	exi_data0(12))
	OR (exi_count(2) AND NOT exi_count(1) AND NOT exi_count(0) AND 
	exi_data0(11))
	OR (NOT exi_count(2) AND exi_count(1) AND NOT exi_count(0) AND 
	exi_data0(9)));


$OpTx$FX_DC$142 <= ((EXP10_.EXP)
	OR (exi_count(2) AND exi_count(1) AND exi_count(0) AND 
	exi_data1(14))
	OR (exi_count(2) AND exi_count(1) AND NOT exi_count(0) AND 
	exi_data1(13))
	OR (exi_count(2) AND NOT exi_count(1) AND exi_count(0) AND 
	exi_data1(12))
	OR (exi_count(2) AND NOT exi_count(1) AND NOT exi_count(0) AND 
	exi_data1(11))
	OR (NOT exi_count(2) AND exi_count(1) AND NOT exi_count(0) AND 
	exi_data1(9)));























FTCPE_do_8bit: FTCPE port map (do_8bit,do_8bit_T,exi_clk,exi_cs,'0');
do_8bit_T <= ((NOT exi_in AND exi_count(4) AND exi_count(3) AND 
	exi_count(2) AND exi_count(1) AND NOT exi_count(0) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND do_write AND NOT do_8bit)
	OR (exi_in AND exi_count(4) AND exi_count(3) AND do_read AND 
	exi_count(2) AND NOT exi_count(1) AND exi_count(0) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND NOT rdmult AND do_8bit));

FTCPE_do_read: FTCPE port map (do_read,do_read_T,exi_clk,exi_cs,'0');
do_read_T <= ((ide_host_data(11).EXP)
	OR (NOT exi_in AND exi_count(4) AND exi_count(3) AND NOT do_read AND 
	exi_count(2) AND exi_count(1) AND exi_count(0) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7)));

FDCPE_do_write: FDCPE port map (do_write,'1',exi_clk,exi_cs,'0',do_write_CE);
do_write_CE <= (exi_in AND exi_count(4) AND exi_count(3) AND 
	exi_count(2) AND exi_count(1) AND exi_count(0) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND NOT rdmult);

FTCPE_exi_address0: FTCPE port map (exi_address(0),exi_address_T(0),exi_clk,'0','0');
exi_address_T(0) <= ((rdmult_cnt(9).EXP)
	OR (NOT exi_cs AND NOT exi_in AND exi_count(4) AND exi_count(3) AND 
	NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	exi_address(0))
	OR (NOT exi_cs AND exi_count(4) AND exi_count(3) AND 
	inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND exi_address(0))
	OR (NOT exi_cs AND exi_count(4) AND exi_count(3) AND 
	NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	rdmult AND exi_address(0))
	OR (NOT exi_cs AND exi_count(4) AND exi_count(3) AND 
	inirdmult AND NOT exi_count(1) AND NOT exi_count(0) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND exi_address(0)));

FTCPE_exi_address1: FTCPE port map (exi_address(1),exi_address_T(1),exi_clk,'0','0');
exi_address_T(1) <= ((rdmult_cnt(10).EXP)
	OR (NOT exi_cs AND exi_count(4) AND exi_count(3) AND 
	inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND exi_address(1))
	OR (NOT exi_cs AND exi_count(4) AND exi_count(3) AND 
	NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	rdmult AND exi_address(1))
	OR (NOT exi_cs AND exi_count(4) AND exi_count(3) AND 
	NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	NOT exi_address(0) AND exi_address(1))
	OR (NOT exi_cs AND exi_count(4) AND exi_count(3) AND 
	inirdmult AND NOT exi_count(1) AND NOT exi_count(0) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND exi_address(1)));

FTCPE_exi_address2: FTCPE port map (exi_address(2),exi_address_T(2),exi_clk,'0','0');
exi_address_T(2) <= ((EXP20_.EXP)
	OR (NOT exi_cs AND exi_count(4) AND exi_count(3) AND 
	inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND exi_address(2))
	OR (NOT exi_cs AND exi_count(4) AND exi_count(3) AND 
	NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	rdmult AND exi_address(2))
	OR (NOT exi_cs AND exi_count(4) AND exi_count(3) AND 
	NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	NOT exi_address(1) AND exi_address(2))
	OR (NOT exi_cs AND exi_count(4) AND exi_count(3) AND 
	inirdmult AND NOT exi_count(1) AND NOT exi_count(0) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND exi_address(2)));

FTCPE_exi_address3: FTCPE port map (exi_address(3),exi_address_T(3),exi_clk,'0','0');
exi_address_T(3) <= ((EXP19_.EXP)
	OR (NOT exi_cs AND exi_count(4) AND exi_count(3) AND 
	inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND exi_address(3))
	OR (NOT exi_cs AND exi_count(4) AND exi_count(3) AND 
	NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	rdmult AND exi_address(3))
	OR (NOT exi_cs AND exi_count(4) AND exi_count(3) AND 
	NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	NOT exi_address(2) AND exi_address(3)));

FTCPE_exi_address4: FTCPE port map (exi_address(4),exi_address_T(4),exi_clk,'0','0');
exi_address_T(4) <= ((EXP12_.EXP)
	OR (NOT exi_cs AND exi_count(4) AND exi_count(3) AND 
	inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT exi_address(4))
	OR (NOT exi_cs AND exi_count(4) AND exi_count(3) AND 
	NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	rdmult AND NOT exi_address(4))
	OR (NOT exi_cs AND exi_count(4) AND exi_count(3) AND 
	NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	exi_address(3) AND NOT exi_address(4))
	OR (NOT exi_cs AND exi_count(4) AND exi_count(3) AND 
	inirdmult AND NOT exi_count(1) AND NOT exi_count(0) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND NOT exi_address(4)));

FTCPE_exi_count0: FTCPE port map (exi_count(0),exi_count_T(0),exi_clk,'0',exi_cs);
exi_count_T(0) <= (NOT exi_count(4) AND exi_count(3) AND exi_count(2) AND 
	exi_count(1) AND exi_count(0) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND do_8bit);

FTCPE_exi_count1: FTCPE port map (exi_count(1),exi_count(0),exi_clk,'0',exi_cs);

FTCPE_exi_count2: FTCPE port map (exi_count(2),exi_count_T(2),exi_clk,'0',exi_cs);
exi_count_T(2) <= (NOT exi_count(1) AND NOT exi_count(0));

FTCPE_exi_count3: FTCPE port map (exi_count(3),exi_count_T(3),exi_clk,'0',exi_cs);
exi_count_T(3) <= ((NOT exi_count(2) AND NOT exi_count(1) AND NOT exi_count(0))
	OR (NOT exi_count(4) AND exi_count(3) AND exi_count(2) AND 
	exi_count(1) AND exi_count(0) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND do_8bit));

FTCPE_exi_count4: FTCPE port map (exi_count(4),exi_count_T(4),exi_clk,'0',exi_cs);
exi_count_T(4) <= (NOT exi_count(3) AND NOT exi_count(2) AND NOT exi_count(1) AND 
	NOT exi_count(0));

FTCPE_exi_count5: FTCPE port map (exi_count(5),exi_count_T(5),exi_clk,exi_cs,'0');
exi_count_T(5) <= (NOT exi_count(4) AND NOT exi_count(3) AND NOT exi_count(2) AND 
	NOT exi_count(1) AND NOT exi_count(0));

FTCPE_exi_count6: FTCPE port map (exi_count(6),exi_count_T(6),exi_clk,exi_cs,'0');
exi_count_T(6) <= (NOT exi_count(4) AND NOT exi_count(3) AND NOT exi_count(2) AND 
	NOT exi_count(1) AND NOT exi_count(0) AND NOT exi_count(5));

FTCPE_exi_count7: FTCPE port map (exi_count(7),exi_count_T(7),exi_clk,exi_cs,'0');
exi_count_T(7) <= (NOT exi_count(4) AND NOT exi_count(3) AND NOT exi_count(2) AND 
	NOT exi_count(1) AND NOT exi_count(0) AND NOT exi_count(5) AND NOT exi_count(6));

FTCPE_exi_data00: FTCPE port map (exi_data0(0),exi_data0_T(0),exi_clk,'0','0',NOT exi_cs);
exi_data0_T(0) <= ((EXP17_.EXP)
	OR (exi_count(4) AND NOT exi_count(3) AND do_read AND 
	NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND exi_data0(0) AND NOT ide_dat(0).PIN)
	OR (exi_count(4) AND NOT exi_count(3) AND do_read AND 
	NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT exi_data0(0) AND ide_dat(0).PIN));

FTCPE_exi_data01: FTCPE port map (exi_data0(1),exi_data0_T(1),exi_clk,'0','0',NOT exi_cs);
exi_data0_T(1) <= ((exi_count(1).EXP)
	OR (exi_count(4) AND NOT exi_count(3) AND do_read AND 
	NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND exi_data0(1) AND NOT ide_dat(1).PIN)
	OR (exi_count(4) AND NOT exi_count(3) AND do_read AND 
	NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT exi_data0(1) AND ide_dat(1).PIN));

FTCPE_exi_data02: FTCPE port map (exi_data0(2),exi_data0_T(2),exi_clk,'0','0',NOT exi_cs);
exi_data0_T(2) <= ((ide_host_data(4).EXP)
	OR (exi_count(4) AND NOT exi_count(3) AND do_read AND 
	NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND exi_data0(2) AND NOT ide_dat(2).PIN)
	OR (exi_count(4) AND NOT exi_count(3) AND do_read AND 
	NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT exi_data0(2) AND ide_dat(2).PIN)
	OR (NOT exi_in AND exi_count(4) AND NOT exi_count(3) AND NOT do_read AND 
	NOT exi_count(2) AND exi_count(1) AND NOT exi_count(0) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND exi_data0(2)));

FTCPE_exi_data03: FTCPE port map (exi_data0(3),exi_data0_T(3),exi_clk,'0','0',NOT exi_cs);
exi_data0_T(3) <= ((ide_host_data(3).EXP)
	OR (exi_count(4) AND NOT exi_count(3) AND do_read AND 
	NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND exi_data0(3) AND NOT ide_dat(3).PIN)
	OR (exi_count(4) AND NOT exi_count(3) AND do_read AND 
	NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT exi_data0(3) AND ide_dat(3).PIN)
	OR (NOT exi_in AND exi_count(4) AND NOT exi_count(3) AND NOT do_read AND 
	NOT exi_count(2) AND exi_count(1) AND exi_count(0) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND exi_data0(3)));

FTCPE_exi_data04: FTCPE port map (exi_data0(4),exi_data0_T(4),exi_clk,'0','0',NOT exi_cs);
exi_data0_T(4) <= ((ide_host_data(2).EXP)
	OR (exi_count(4) AND NOT exi_count(3) AND do_read AND 
	NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND exi_data0(4) AND NOT ide_dat(4).PIN)
	OR (exi_count(4) AND NOT exi_count(3) AND do_read AND 
	NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT exi_data0(4) AND ide_dat(4).PIN)
	OR (NOT exi_in AND exi_count(4) AND NOT exi_count(3) AND NOT do_read AND 
	exi_count(2) AND NOT exi_count(1) AND NOT exi_count(0) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND exi_data0(4)));

FTCPE_exi_data05: FTCPE port map (exi_data0(5),exi_data0_T(5),exi_clk,'0','0',NOT exi_cs);
exi_data0_T(5) <= ((ide_host_data(1).EXP)
	OR (exi_count(4) AND NOT exi_count(3) AND do_read AND 
	NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND exi_data0(5) AND NOT ide_dat(5).PIN)
	OR (exi_count(4) AND NOT exi_count(3) AND do_read AND 
	NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT exi_data0(5) AND ide_dat(5).PIN)
	OR (NOT exi_in AND exi_count(4) AND NOT exi_count(3) AND NOT do_read AND 
	exi_count(2) AND NOT exi_count(1) AND exi_count(0) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND exi_data0(5)));

FTCPE_exi_data06: FTCPE port map (exi_data0(6),exi_data0_T(6),exi_clk,'0','0',NOT exi_cs);
exi_data0_T(6) <= ((ide_host_data(14).EXP)
	OR (exi_count(4) AND NOT exi_count(3) AND do_read AND 
	NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND exi_data0(6) AND NOT ide_dat(6).PIN)
	OR (exi_count(4) AND NOT exi_count(3) AND do_read AND 
	NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT exi_data0(6) AND ide_dat(6).PIN)
	OR (NOT exi_in AND exi_count(4) AND NOT exi_count(3) AND NOT do_read AND 
	exi_count(2) AND exi_count(1) AND NOT exi_count(0) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND exi_data0(6)));

FTCPE_exi_data07: FTCPE port map (exi_data0(7),exi_data0_T(7),exi_clk,'0','0',NOT exi_cs);
exi_data0_T(7) <= ((ide_host_data(15).EXP)
	OR (exi_count(4) AND NOT exi_count(3) AND do_read AND 
	NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND exi_data0(7) AND NOT ide_dat(7).PIN)
	OR (exi_count(4) AND NOT exi_count(3) AND do_read AND 
	NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT exi_data0(7) AND ide_dat(7).PIN)
	OR (NOT exi_in AND exi_count(4) AND NOT exi_count(3) AND NOT do_read AND 
	exi_count(2) AND exi_count(1) AND exi_count(0) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND exi_data0(7)));

FTCPE_exi_data08: FTCPE port map (exi_data0(8),exi_data0_T(8),exi_clk,'0','0',NOT exi_cs);
exi_data0_T(8) <= ((exi_data0(9).EXP)
	OR (ide_dat(8).PIN AND exi_count(4) AND NOT exi_count(3) AND 
	do_read AND NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND NOT exi_data0(8))
	OR (NOT ide_dat(8).PIN AND exi_count(4) AND NOT exi_count(3) AND 
	do_read AND NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND exi_data0(8))
	OR (NOT exi_in AND NOT exi_count(4) AND exi_count(3) AND NOT do_read AND 
	NOT exi_count(2) AND NOT exi_count(1) AND NOT exi_count(0) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND exi_data0(8)));

FTCPE_exi_data09: FTCPE port map (exi_data0(9),exi_data0_T(9),exi_clk,'0','0',NOT exi_cs);
exi_data0_T(9) <= ((do_read.EXP)
	OR (ide_dat(9).PIN AND exi_count(4) AND NOT exi_count(3) AND 
	do_read AND NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND NOT exi_data0(9))
	OR (NOT ide_dat(9).PIN AND exi_count(4) AND NOT exi_count(3) AND 
	do_read AND NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND exi_data0(9)));

FTCPE_exi_data010: FTCPE port map (exi_data0(10),exi_data0_T(10),exi_clk,'0','0',NOT exi_cs);
exi_data0_T(10) <= ((rdmult_cnt(5).EXP)
	OR (ide_dat(10).PIN AND exi_count(4) AND NOT exi_count(3) AND 
	do_read AND NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND NOT exi_data0(10))
	OR (NOT ide_dat(10).PIN AND exi_count(4) AND NOT exi_count(3) AND 
	do_read AND NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND exi_data0(10))
	OR (NOT exi_in AND NOT exi_count(4) AND exi_count(3) AND NOT do_read AND 
	NOT exi_count(2) AND exi_count(1) AND NOT exi_count(0) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND exi_data0(10)));

FTCPE_exi_data011: FTCPE port map (exi_data0(11),exi_data0_T(11),exi_clk,'0','0',NOT exi_cs);
exi_data0_T(11) <= ((ide_host_data(5).EXP)
	OR (ide_dat(11).PIN AND exi_count(4) AND NOT exi_count(3) AND 
	do_read AND NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND NOT exi_data0(11))
	OR (NOT ide_dat(11).PIN AND exi_count(4) AND NOT exi_count(3) AND 
	do_read AND NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND exi_data0(11))
	OR (NOT exi_in AND NOT exi_count(4) AND exi_count(3) AND NOT do_read AND 
	NOT exi_count(2) AND exi_count(1) AND exi_count(0) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND exi_data0(11)));

FTCPE_exi_data012: FTCPE port map (exi_data0(12),exi_data0_T(12),exi_clk,'0','0',NOT exi_cs);
exi_data0_T(12) <= ((ide_host_data(12).EXP)
	OR (ide_dat(12).PIN AND exi_count(4) AND NOT exi_count(3) AND 
	do_read AND NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND NOT exi_data0(12))
	OR (NOT ide_dat(12).PIN AND exi_count(4) AND NOT exi_count(3) AND 
	do_read AND NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND exi_data0(12)));

FTCPE_exi_data013: FTCPE port map (exi_data0(13),exi_data0_T(13),exi_clk,'0','0',NOT exi_cs);
exi_data0_T(13) <= ((exi_data0(12).EXP)
	OR (ide_dat(13).PIN AND exi_count(4) AND NOT exi_count(3) AND 
	do_read AND NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND NOT exi_data0(13))
	OR (NOT ide_dat(13).PIN AND exi_count(4) AND NOT exi_count(3) AND 
	do_read AND NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND exi_data0(13))
	OR (NOT exi_in AND NOT exi_count(4) AND exi_count(3) AND NOT do_read AND 
	exi_count(2) AND NOT exi_count(1) AND exi_count(0) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND exi_data0(13)));

FTCPE_exi_data014: FTCPE port map (exi_data0(14),exi_data0_T(14),exi_clk,'0','0',NOT exi_cs);
exi_data0_T(14) <= ((ide_host_data(13).EXP)
	OR (ide_dat(14).PIN AND exi_count(4) AND NOT exi_count(3) AND 
	do_read AND NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND NOT exi_data0(14))
	OR (NOT ide_dat(14).PIN AND exi_count(4) AND NOT exi_count(3) AND 
	do_read AND NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND exi_data0(14))
	OR (NOT exi_in AND NOT exi_count(4) AND exi_count(3) AND NOT do_read AND 
	exi_count(2) AND exi_count(1) AND NOT exi_count(0) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND exi_data0(14)));

FTCPE_exi_data015: FTCPE port map (exi_data0(15),exi_data0_T(15),exi_clk,'0','0',NOT exi_cs);
exi_data0_T(15) <= ((EXP18_.EXP)
	OR (ide_dat(15).PIN AND exi_count(4) AND NOT exi_count(3) AND 
	do_read AND NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND NOT exi_data0(15))
	OR (NOT ide_dat(15).PIN AND exi_count(4) AND NOT exi_count(3) AND 
	do_read AND NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND exi_data0(15))
	OR (NOT exi_in AND NOT exi_count(4) AND exi_count(3) AND NOT do_read AND 
	exi_count(2) AND exi_count(1) AND exi_count(0) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND exi_data0(15)));

FTCPE_exi_data10: FTCPE port map (exi_data1(0),exi_data1_T(0),exi_clk,'0','0');
exi_data1_T(0) <= ((NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT do_write AND ide_dat(0).PIN AND NOT exi_data1(0))
	OR (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT do_write AND NOT ide_dat(0).PIN AND exi_data1(0))
	OR (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	NOT do_write AND rdmult AND ide_dat(0).PIN AND NOT exi_data1(0))
	OR (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	NOT do_write AND rdmult AND NOT ide_dat(0).PIN AND exi_data1(0)));

FTCPE_exi_data11: FTCPE port map (exi_data1(1),exi_data1_T(1),exi_clk,'0','0');
exi_data1_T(1) <= ((NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT do_write AND ide_dat(1).PIN AND NOT exi_data1(1))
	OR (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT do_write AND NOT ide_dat(1).PIN AND exi_data1(1))
	OR (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	NOT do_write AND rdmult AND ide_dat(1).PIN AND NOT exi_data1(1))
	OR (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	NOT do_write AND rdmult AND NOT ide_dat(1).PIN AND exi_data1(1)));

FTCPE_exi_data12: FTCPE port map (exi_data1(2),exi_data1_T(2),exi_clk,'0','0');
exi_data1_T(2) <= ((NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT do_write AND ide_dat(2).PIN AND NOT exi_data1(2))
	OR (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT do_write AND NOT ide_dat(2).PIN AND exi_data1(2))
	OR (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	NOT do_write AND rdmult AND ide_dat(2).PIN AND NOT exi_data1(2))
	OR (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	NOT do_write AND rdmult AND NOT ide_dat(2).PIN AND exi_data1(2)));

FTCPE_exi_data13: FTCPE port map (exi_data1(3),exi_data1_T(3),exi_clk,'0','0');
exi_data1_T(3) <= ((NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT do_write AND ide_dat(3).PIN AND NOT exi_data1(3))
	OR (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT do_write AND NOT ide_dat(3).PIN AND exi_data1(3))
	OR (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	NOT do_write AND rdmult AND ide_dat(3).PIN AND NOT exi_data1(3))
	OR (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	NOT do_write AND rdmult AND NOT ide_dat(3).PIN AND exi_data1(3)));

FTCPE_exi_data14: FTCPE port map (exi_data1(4),exi_data1_T(4),exi_clk,'0','0');
exi_data1_T(4) <= ((NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT do_write AND ide_dat(4).PIN AND NOT exi_data1(4))
	OR (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT do_write AND NOT ide_dat(4).PIN AND exi_data1(4))
	OR (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	NOT do_write AND rdmult AND ide_dat(4).PIN AND NOT exi_data1(4))
	OR (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	NOT do_write AND rdmult AND NOT ide_dat(4).PIN AND exi_data1(4)));

FTCPE_exi_data15: FTCPE port map (exi_data1(5),exi_data1_T(5),exi_clk,'0','0');
exi_data1_T(5) <= ((NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT do_write AND ide_dat(5).PIN AND NOT exi_data1(5))
	OR (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT do_write AND NOT ide_dat(5).PIN AND exi_data1(5))
	OR (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	NOT do_write AND rdmult AND ide_dat(5).PIN AND NOT exi_data1(5))
	OR (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	NOT do_write AND rdmult AND NOT ide_dat(5).PIN AND exi_data1(5)));

FTCPE_exi_data16: FTCPE port map (exi_data1(6),exi_data1_T(6),exi_clk,'0','0');
exi_data1_T(6) <= ((NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT do_write AND ide_dat(6).PIN AND NOT exi_data1(6))
	OR (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT do_write AND NOT ide_dat(6).PIN AND exi_data1(6))
	OR (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	NOT do_write AND rdmult AND ide_dat(6).PIN AND NOT exi_data1(6))
	OR (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	NOT do_write AND rdmult AND NOT ide_dat(6).PIN AND exi_data1(6)));

FTCPE_exi_data17: FTCPE port map (exi_data1(7),exi_data1_T(7),exi_clk,'0','0');
exi_data1_T(7) <= ((NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT do_write AND ide_dat(7).PIN AND NOT exi_data1(7))
	OR (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT do_write AND NOT ide_dat(7).PIN AND exi_data1(7))
	OR (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	NOT do_write AND rdmult AND ide_dat(7).PIN AND NOT exi_data1(7))
	OR (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	NOT do_write AND rdmult AND NOT ide_dat(7).PIN AND exi_data1(7)));

FTCPE_exi_data18: FTCPE port map (exi_data1(8),exi_data1_T(8),exi_clk,'0','0');
exi_data1_T(8) <= ((NOT exi_cs AND ide_dat(8).PIN AND NOT exi_count(4) AND 
	NOT exi_count(3) AND inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND NOT do_write AND NOT exi_data1(8))
	OR (NOT exi_cs AND ide_dat(8).PIN AND NOT exi_count(4) AND 
	NOT exi_count(3) AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT do_write AND rdmult AND NOT exi_data1(8))
	OR (NOT exi_cs AND NOT ide_dat(8).PIN AND NOT exi_count(4) AND 
	NOT exi_count(3) AND inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND NOT do_write AND exi_data1(8))
	OR (NOT exi_cs AND NOT ide_dat(8).PIN AND NOT exi_count(4) AND 
	NOT exi_count(3) AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT do_write AND rdmult AND exi_data1(8)));

FTCPE_exi_data19: FTCPE port map (exi_data1(9),exi_data1_T(9),exi_clk,'0','0');
exi_data1_T(9) <= ((NOT exi_cs AND ide_dat(9).PIN AND NOT exi_count(4) AND 
	NOT exi_count(3) AND inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND NOT do_write AND NOT exi_data1(9))
	OR (NOT exi_cs AND ide_dat(9).PIN AND NOT exi_count(4) AND 
	NOT exi_count(3) AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT do_write AND rdmult AND NOT exi_data1(9))
	OR (NOT exi_cs AND NOT ide_dat(9).PIN AND NOT exi_count(4) AND 
	NOT exi_count(3) AND inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND NOT do_write AND exi_data1(9))
	OR (NOT exi_cs AND NOT ide_dat(9).PIN AND NOT exi_count(4) AND 
	NOT exi_count(3) AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT do_write AND rdmult AND exi_data1(9)));

FTCPE_exi_data110: FTCPE port map (exi_data1(10),exi_data1_T(10),exi_clk,'0','0');
exi_data1_T(10) <= ((NOT exi_cs AND ide_dat(10).PIN AND NOT exi_count(4) AND 
	NOT exi_count(3) AND inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND NOT do_write AND NOT exi_data1(10))
	OR (NOT exi_cs AND ide_dat(10).PIN AND NOT exi_count(4) AND 
	NOT exi_count(3) AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT do_write AND rdmult AND NOT exi_data1(10))
	OR (NOT exi_cs AND NOT ide_dat(10).PIN AND NOT exi_count(4) AND 
	NOT exi_count(3) AND inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND NOT do_write AND exi_data1(10))
	OR (NOT exi_cs AND NOT ide_dat(10).PIN AND NOT exi_count(4) AND 
	NOT exi_count(3) AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT do_write AND rdmult AND exi_data1(10)));

FTCPE_exi_data111: FTCPE port map (exi_data1(11),exi_data1_T(11),exi_clk,'0','0');
exi_data1_T(11) <= ((NOT exi_cs AND ide_dat(11).PIN AND NOT exi_count(4) AND 
	NOT exi_count(3) AND inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND NOT do_write AND NOT exi_data1(11))
	OR (NOT exi_cs AND ide_dat(11).PIN AND NOT exi_count(4) AND 
	NOT exi_count(3) AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT do_write AND rdmult AND NOT exi_data1(11))
	OR (NOT exi_cs AND NOT ide_dat(11).PIN AND NOT exi_count(4) AND 
	NOT exi_count(3) AND inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND NOT do_write AND exi_data1(11))
	OR (NOT exi_cs AND NOT ide_dat(11).PIN AND NOT exi_count(4) AND 
	NOT exi_count(3) AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT do_write AND rdmult AND exi_data1(11)));

FTCPE_exi_data112: FTCPE port map (exi_data1(12),exi_data1_T(12),exi_clk,'0','0');
exi_data1_T(12) <= ((NOT exi_cs AND ide_dat(12).PIN AND NOT exi_count(4) AND 
	NOT exi_count(3) AND inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND NOT do_write AND NOT exi_data1(12))
	OR (NOT exi_cs AND ide_dat(12).PIN AND NOT exi_count(4) AND 
	NOT exi_count(3) AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT do_write AND rdmult AND NOT exi_data1(12))
	OR (NOT exi_cs AND NOT ide_dat(12).PIN AND NOT exi_count(4) AND 
	NOT exi_count(3) AND inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND NOT do_write AND exi_data1(12))
	OR (NOT exi_cs AND NOT ide_dat(12).PIN AND NOT exi_count(4) AND 
	NOT exi_count(3) AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT do_write AND rdmult AND exi_data1(12)));

FTCPE_exi_data113: FTCPE port map (exi_data1(13),exi_data1_T(13),exi_clk,'0','0');
exi_data1_T(13) <= ((NOT exi_cs AND ide_dat(13).PIN AND NOT exi_count(4) AND 
	NOT exi_count(3) AND inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND NOT do_write AND NOT exi_data1(13))
	OR (NOT exi_cs AND ide_dat(13).PIN AND NOT exi_count(4) AND 
	NOT exi_count(3) AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT do_write AND rdmult AND NOT exi_data1(13))
	OR (NOT exi_cs AND NOT ide_dat(13).PIN AND NOT exi_count(4) AND 
	NOT exi_count(3) AND inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND NOT do_write AND exi_data1(13))
	OR (NOT exi_cs AND NOT ide_dat(13).PIN AND NOT exi_count(4) AND 
	NOT exi_count(3) AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT do_write AND rdmult AND exi_data1(13)));

FTCPE_exi_data114: FTCPE port map (exi_data1(14),exi_data1_T(14),exi_clk,'0','0');
exi_data1_T(14) <= ((NOT exi_cs AND ide_dat(14).PIN AND NOT exi_count(4) AND 
	NOT exi_count(3) AND inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND NOT do_write AND NOT exi_data1(14))
	OR (NOT exi_cs AND ide_dat(14).PIN AND NOT exi_count(4) AND 
	NOT exi_count(3) AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT do_write AND rdmult AND NOT exi_data1(14))
	OR (NOT exi_cs AND NOT ide_dat(14).PIN AND NOT exi_count(4) AND 
	NOT exi_count(3) AND inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND NOT do_write AND exi_data1(14))
	OR (NOT exi_cs AND NOT ide_dat(14).PIN AND NOT exi_count(4) AND 
	NOT exi_count(3) AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT do_write AND rdmult AND exi_data1(14)));

FTCPE_exi_data115: FTCPE port map (exi_data1(15),exi_data1_T(15),exi_clk,'0','0');
exi_data1_T(15) <= ((NOT exi_cs AND ide_dat(15).PIN AND NOT exi_count(4) AND 
	NOT exi_count(3) AND inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND NOT do_write AND NOT exi_data1(15))
	OR (NOT exi_cs AND ide_dat(15).PIN AND NOT exi_count(4) AND 
	NOT exi_count(3) AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT do_write AND rdmult AND NOT exi_data1(15))
	OR (NOT exi_cs AND NOT ide_dat(15).PIN AND NOT exi_count(4) AND 
	NOT exi_count(3) AND inirdmult AND NOT exi_count(2) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND NOT do_write AND exi_data1(15))
	OR (NOT exi_cs AND NOT ide_dat(15).PIN AND NOT exi_count(4) AND 
	NOT exi_count(3) AND NOT exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT do_write AND rdmult AND exi_data1(15)));

FDCPE_exi_out: FDCPE port map (exi_out_I,exi_out,exi_clk,'0','0',NOT exi_cs);
exi_out <= ((EXP13_.EXP)
	OR (EXP14_.EXP)
	OR (exi_out AND exi_count(5))
	OR (exi_out AND exi_count(7)));
exi_out <= exi_out_I when exi_out_OE = '1' else 'Z';
exi_out_OE <= NOT exi_cs;


ide_adr(0) <= (NOT exi_cs AND exi_address(0));


ide_adr(1) <= (NOT exi_cs AND exi_address(1));


ide_adr(2) <= (NOT exi_cs AND exi_address(2));


ide_adr(3) <= (NOT exi_cs AND exi_address(3));


ide_adr(4) <= (NOT exi_cs AND exi_address(4));

FDCPE_ide_dat0: FDCPE port map (ide_dat_I(0),exi_data0(0),exi_clk,'0','0',ide_dat_CE(0));
ide_dat_CE(0) <= (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	do_write);
ide_dat(0) <= ide_dat_I(0) when ide_dat_OE(0) = '1' else 'Z';
ide_dat_OE(0) <= NOT ide_wr;

FDCPE_ide_dat1: FDCPE port map (ide_dat_I(1),exi_data0(1),exi_clk,'0','0',ide_dat_CE(1));
ide_dat_CE(1) <= (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	do_write);
ide_dat(1) <= ide_dat_I(1) when ide_dat_OE(1) = '1' else 'Z';
ide_dat_OE(1) <= NOT ide_wr;

FDCPE_ide_dat2: FDCPE port map (ide_dat_I(2),exi_data0(2),exi_clk,'0','0',ide_dat_CE(2));
ide_dat_CE(2) <= (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	do_write);
ide_dat(2) <= ide_dat_I(2) when ide_dat_OE(2) = '1' else 'Z';
ide_dat_OE(2) <= NOT ide_wr;

FDCPE_ide_dat3: FDCPE port map (ide_dat_I(3),exi_data0(3),exi_clk,'0','0',ide_dat_CE(3));
ide_dat_CE(3) <= (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	do_write);
ide_dat(3) <= ide_dat_I(3) when ide_dat_OE(3) = '1' else 'Z';
ide_dat_OE(3) <= NOT ide_wr;

FDCPE_ide_dat4: FDCPE port map (ide_dat_I(4),exi_data0(4),exi_clk,'0','0',ide_dat_CE(4));
ide_dat_CE(4) <= (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	do_write);
ide_dat(4) <= ide_dat_I(4) when ide_dat_OE(4) = '1' else 'Z';
ide_dat_OE(4) <= NOT ide_wr;

FDCPE_ide_dat5: FDCPE port map (ide_dat_I(5),exi_data0(5),exi_clk,'0','0',ide_dat_CE(5));
ide_dat_CE(5) <= (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	do_write);
ide_dat(5) <= ide_dat_I(5) when ide_dat_OE(5) = '1' else 'Z';
ide_dat_OE(5) <= NOT ide_wr;

FDCPE_ide_dat6: FDCPE port map (ide_dat_I(6),exi_data0(6),exi_clk,'0','0',ide_dat_CE(6));
ide_dat_CE(6) <= (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	do_write);
ide_dat(6) <= ide_dat_I(6) when ide_dat_OE(6) = '1' else 'Z';
ide_dat_OE(6) <= NOT ide_wr;

FDCPE_ide_dat7: FDCPE port map (ide_dat_I(7),exi_data0(7),exi_clk,'0','0',ide_dat_CE(7));
ide_dat_CE(7) <= (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	do_write);
ide_dat(7) <= ide_dat_I(7) when ide_dat_OE(7) = '1' else 'Z';
ide_dat_OE(7) <= NOT ide_wr;

FDCPE_ide_dat8: FDCPE port map (ide_dat_I(8),exi_data0(8),exi_clk,'0','0',ide_dat_CE(8));
ide_dat_CE(8) <= (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	do_write);
ide_dat(8) <= ide_dat_I(8) when ide_dat_OE(8) = '1' else 'Z';
ide_dat_OE(8) <= NOT ide_wr;

FDCPE_ide_dat9: FDCPE port map (ide_dat_I(9),exi_data0(9),exi_clk,'0','0',ide_dat_CE(9));
ide_dat_CE(9) <= (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	do_write);
ide_dat(9) <= ide_dat_I(9) when ide_dat_OE(9) = '1' else 'Z';
ide_dat_OE(9) <= NOT ide_wr;

FDCPE_ide_dat10: FDCPE port map (ide_dat_I(10),exi_data0(10),exi_clk,'0','0',ide_dat_CE(10));
ide_dat_CE(10) <= (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	do_write);
ide_dat(10) <= ide_dat_I(10) when ide_dat_OE(10) = '1' else 'Z';
ide_dat_OE(10) <= NOT ide_wr;

FDCPE_ide_dat11: FDCPE port map (ide_dat_I(11),exi_data0(11),exi_clk,'0','0',ide_dat_CE(11));
ide_dat_CE(11) <= (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	do_write);
ide_dat(11) <= ide_dat_I(11) when ide_dat_OE(11) = '1' else 'Z';
ide_dat_OE(11) <= NOT ide_wr;

FDCPE_ide_dat12: FDCPE port map (ide_dat_I(12),exi_address(3).EXP,exi_clk,'0','0',ide_dat_CE(12));
ide_dat_CE(12) <= (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	do_write);
ide_dat(12) <= ide_dat_I(12) when ide_dat_OE(12) = '1' else 'Z';
ide_dat_OE(12) <= NOT ide_wr;

FDCPE_ide_dat13: FDCPE port map (ide_dat_I(13),exi_data0(13),exi_clk,'0','0',ide_dat_CE(13));
ide_dat_CE(13) <= (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	do_write);
ide_dat(13) <= ide_dat_I(13) when ide_dat_OE(13) = '1' else 'Z';
ide_dat_OE(13) <= NOT ide_wr;

FDCPE_ide_dat14: FDCPE port map (ide_dat_I(14),exi_data0(14),exi_clk,'0','0',ide_dat_CE(14));
ide_dat_CE(14) <= (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	do_write);
ide_dat(14) <= ide_dat_I(14) when ide_dat_OE(14) = '1' else 'Z';
ide_dat_OE(14) <= NOT ide_wr;

FDCPE_ide_dat15: FDCPE port map (ide_dat_I(15),exi_data0(15),exi_clk,'0','0',ide_dat_CE(15));
ide_dat_CE(15) <= (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	do_write);
ide_dat(15) <= ide_dat_I(15) when ide_dat_OE(15) = '1' else 'Z';
ide_dat_OE(15) <= NOT ide_wr;

FTCPE_ide_rd: FTCPE port map (ide_rd,ide_rd_T,exi_clk,'0',exi_cs);
ide_rd_T <= ((do_8bit.EXP)
	OR (rdmult.EXP)
	OR (ide_rd AND exi_count(4) AND NOT exi_count(3) AND do_read AND 
	NOT inirdmult AND exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7))
	OR (ide_rd AND NOT exi_count(4) AND NOT exi_count(3) AND 
	inirdmult AND exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND 
	NOT exi_count(7) AND NOT do_write)
	OR (ide_rd AND NOT exi_count(4) AND NOT exi_count(3) AND 
	exi_count(2) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	NOT do_write AND rdmult));

FDCPE_ide_wr: FDCPE port map (ide_wr,ide_wr_D,exi_clk,'0',exi_cs,ide_wr_CE);
ide_wr_D <= (NOT exi_count(4) AND NOT exi_count(3) AND NOT exi_count(2) AND 
	NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7));
ide_wr_CE <= (NOT exi_count(4) AND NOT exi_count(3) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND do_write);

FDCPE_inirdmult: FDCPE port map (inirdmult,'1',exi_clk,exi_cs,'0',inirdmult_CE);
inirdmult_CE <= (exi_in AND exi_count(4) AND exi_count(3) AND do_read AND 
	exi_count(2) AND NOT exi_count(1) AND exi_count(0) AND NOT exi_count(5) AND 
	NOT exi_count(6) AND NOT exi_count(7) AND NOT rdmult);

FTCPE_rdmult: FTCPE port map (rdmult,rdmult_T,exi_clk,'0','0');
rdmult_T <= ((NOT exi_cs AND inirdmult AND NOT rdmult)
	OR (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(1) AND NOT exi_count(0) AND 
	NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND rdmult AND 
	NOT rdmult_cnt(0) AND NOT rdmult_cnt(10) AND NOT rdmult_cnt(11) AND NOT rdmult_cnt(12) AND 
	NOT rdmult_cnt(13) AND NOT rdmult_cnt(14) AND NOT rdmult_cnt(1) AND NOT rdmult_cnt(2) AND 
	NOT rdmult_cnt(3) AND NOT rdmult_cnt(4) AND NOT rdmult_cnt(5) AND NOT rdmult_cnt(6) AND 
	NOT rdmult_cnt(7) AND NOT rdmult_cnt(8) AND NOT rdmult_cnt(9) AND NOT rdmult_cnt(15)));

FTCPE_rdmult_cnt0: FTCPE port map (rdmult_cnt(0),rdmult_cnt_T(0),exi_clk,'0','0');
rdmult_cnt_T(0) <= ((NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(1) AND NOT exi_count(0) AND 
	NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7))
	OR (NOT exi_cs AND exi_in AND exi_count(4) AND NOT exi_count(3) AND 
	do_read AND inirdmult AND NOT exi_count(2) AND NOT exi_count(1) AND 
	NOT exi_count(0) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	NOT rdmult_cnt(0))
	OR (NOT exi_cs AND NOT exi_in AND exi_count(4) AND NOT exi_count(3) AND 
	do_read AND inirdmult AND NOT exi_count(2) AND NOT exi_count(1) AND 
	NOT exi_count(0) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	rdmult_cnt(0)));

FTCPE_rdmult_cnt1: FTCPE port map (rdmult_cnt(1),rdmult_cnt_T(1),exi_clk,'0','0');
rdmult_cnt_T(1) <= ((NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(1) AND NOT exi_count(0) AND 
	NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND NOT rdmult_cnt(0))
	OR (NOT exi_cs AND exi_in AND exi_count(4) AND NOT exi_count(3) AND 
	do_read AND inirdmult AND NOT exi_count(2) AND NOT exi_count(1) AND 
	exi_count(0) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	NOT rdmult_cnt(1))
	OR (NOT exi_cs AND NOT exi_in AND exi_count(4) AND NOT exi_count(3) AND 
	do_read AND inirdmult AND NOT exi_count(2) AND NOT exi_count(1) AND 
	exi_count(0) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	rdmult_cnt(1)));

FTCPE_rdmult_cnt2: FTCPE port map (rdmult_cnt(2),rdmult_cnt_T(2),exi_clk,'0','0');
rdmult_cnt_T(2) <= ((NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(1) AND NOT exi_count(0) AND 
	NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND NOT rdmult_cnt(0) AND 
	NOT rdmult_cnt(1))
	OR (NOT exi_cs AND exi_in AND exi_count(4) AND NOT exi_count(3) AND 
	do_read AND inirdmult AND NOT exi_count(2) AND exi_count(1) AND 
	NOT exi_count(0) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	NOT rdmult_cnt(2))
	OR (NOT exi_cs AND NOT exi_in AND exi_count(4) AND NOT exi_count(3) AND 
	do_read AND inirdmult AND NOT exi_count(2) AND exi_count(1) AND 
	NOT exi_count(0) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	rdmult_cnt(2)));

FTCPE_rdmult_cnt3: FTCPE port map (rdmult_cnt(3),rdmult_cnt_T(3),exi_clk,'0','0');
rdmult_cnt_T(3) <= ((NOT exi_cs AND exi_in AND exi_count(4) AND NOT exi_count(3) AND 
	do_read AND inirdmult AND NOT exi_count(2) AND exi_count(1) AND 
	exi_count(0) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	NOT rdmult_cnt(3))
	OR (NOT exi_cs AND NOT exi_in AND exi_count(4) AND NOT exi_count(3) AND 
	do_read AND inirdmult AND NOT exi_count(2) AND exi_count(1) AND 
	exi_count(0) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	rdmult_cnt(3))
	OR (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(1) AND NOT exi_count(0) AND 
	NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND NOT rdmult_cnt(0) AND 
	NOT rdmult_cnt(1) AND NOT rdmult_cnt(2)));

FTCPE_rdmult_cnt4: FTCPE port map (rdmult_cnt(4),rdmult_cnt_T(4),exi_clk,'0','0');
rdmult_cnt_T(4) <= ((NOT exi_cs AND exi_in AND exi_count(4) AND NOT exi_count(3) AND 
	do_read AND inirdmult AND exi_count(2) AND NOT exi_count(1) AND 
	NOT exi_count(0) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	NOT rdmult_cnt(4))
	OR (NOT exi_cs AND NOT exi_in AND exi_count(4) AND NOT exi_count(3) AND 
	do_read AND inirdmult AND exi_count(2) AND NOT exi_count(1) AND 
	NOT exi_count(0) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	rdmult_cnt(4))
	OR (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(1) AND NOT exi_count(0) AND 
	NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND NOT rdmult_cnt(0) AND 
	NOT rdmult_cnt(1) AND NOT rdmult_cnt(2) AND NOT rdmult_cnt(3)));

FTCPE_rdmult_cnt5: FTCPE port map (rdmult_cnt(5),rdmult_cnt_T(5),exi_clk,'0','0');
rdmult_cnt_T(5) <= ((NOT exi_cs AND exi_in AND exi_count(4) AND NOT exi_count(3) AND 
	do_read AND inirdmult AND exi_count(2) AND NOT exi_count(1) AND 
	exi_count(0) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	NOT rdmult_cnt(5))
	OR (NOT exi_cs AND NOT exi_in AND exi_count(4) AND NOT exi_count(3) AND 
	do_read AND inirdmult AND exi_count(2) AND NOT exi_count(1) AND 
	exi_count(0) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	rdmult_cnt(5))
	OR (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(1) AND NOT exi_count(0) AND 
	NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND NOT rdmult_cnt(0) AND 
	NOT rdmult_cnt(1) AND NOT rdmult_cnt(2) AND NOT rdmult_cnt(3) AND NOT rdmult_cnt(4)));

FTCPE_rdmult_cnt6: FTCPE port map (rdmult_cnt(6),rdmult_cnt_T(6),exi_clk,'0','0');
rdmult_cnt_T(6) <= ((NOT exi_cs AND exi_in AND exi_count(4) AND NOT exi_count(3) AND 
	do_read AND inirdmult AND exi_count(2) AND exi_count(1) AND 
	NOT exi_count(0) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	NOT rdmult_cnt(6))
	OR (NOT exi_cs AND NOT exi_in AND exi_count(4) AND NOT exi_count(3) AND 
	do_read AND inirdmult AND exi_count(2) AND exi_count(1) AND 
	NOT exi_count(0) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	rdmult_cnt(6))
	OR (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(1) AND NOT exi_count(0) AND 
	NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND NOT rdmult_cnt(0) AND 
	NOT rdmult_cnt(1) AND NOT rdmult_cnt(2) AND NOT rdmult_cnt(3) AND NOT rdmult_cnt(4) AND 
	NOT rdmult_cnt(5)));

FTCPE_rdmult_cnt7: FTCPE port map (rdmult_cnt(7),rdmult_cnt_T(7),exi_clk,'0','0');
rdmult_cnt_T(7) <= ((ide_adr_1_OBUF.EXP)
	OR (NOT exi_cs AND exi_in AND exi_count(4) AND NOT exi_count(3) AND 
	do_read AND inirdmult AND exi_count(2) AND exi_count(1) AND 
	exi_count(0) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	NOT rdmult_cnt(7))
	OR (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(1) AND NOT exi_count(0) AND 
	NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND NOT rdmult_cnt(0) AND 
	NOT rdmult_cnt(1) AND NOT rdmult_cnt(2) AND NOT rdmult_cnt(3) AND NOT rdmult_cnt(4) AND 
	NOT rdmult_cnt(5) AND NOT rdmult_cnt(6)));

FTCPE_rdmult_cnt8: FTCPE port map (rdmult_cnt(8),rdmult_cnt_T(8),exi_clk,'0','0');
rdmult_cnt_T(8) <= ((rdmult_cnt(7).EXP)
	OR (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(1) AND NOT exi_count(0) AND 
	NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND NOT rdmult_cnt(0) AND 
	NOT rdmult_cnt(1) AND NOT rdmult_cnt(2) AND NOT rdmult_cnt(3) AND NOT rdmult_cnt(4) AND 
	NOT rdmult_cnt(5) AND NOT rdmult_cnt(6) AND NOT rdmult_cnt(7)));

FTCPE_rdmult_cnt9: FTCPE port map (rdmult_cnt(9),rdmult_cnt(8).EXP,exi_clk,'0','0');

FTCPE_rdmult_cnt10: FTCPE port map (rdmult_cnt(10),rdmult_cnt(11).EXP,exi_clk,'0','0');

FTCPE_rdmult_cnt11: FTCPE port map (rdmult_cnt(11),rdmult_cnt_T(11),exi_clk,'0','0');
rdmult_cnt_T(11) <= ((ide_adr_3_OBUF.EXP)
	OR (NOT exi_cs AND exi_in AND NOT exi_count(4) AND exi_count(3) AND 
	do_read AND inirdmult AND NOT exi_count(2) AND exi_count(1) AND 
	exi_count(0) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	NOT rdmult_cnt(11)));

FTCPE_rdmult_cnt12: FTCPE port map (rdmult_cnt(12),rdmult_cnt_T(12),exi_clk,'0','0');
rdmult_cnt_T(12) <= ((NOT exi_cs AND exi_in AND NOT exi_count(4) AND exi_count(3) AND 
	do_read AND inirdmult AND exi_count(2) AND NOT exi_count(1) AND 
	NOT exi_count(0) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	NOT rdmult_cnt(12))
	OR (NOT exi_cs AND NOT exi_in AND NOT exi_count(4) AND exi_count(3) AND 
	do_read AND inirdmult AND exi_count(2) AND NOT exi_count(1) AND 
	NOT exi_count(0) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	rdmult_cnt(12))
	OR (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(1) AND NOT exi_count(0) AND 
	NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND NOT rdmult_cnt(0) AND 
	NOT rdmult_cnt(10) AND NOT rdmult_cnt(11) AND NOT rdmult_cnt(1) AND NOT rdmult_cnt(2) AND 
	NOT rdmult_cnt(3) AND NOT rdmult_cnt(4) AND NOT rdmult_cnt(5) AND NOT rdmult_cnt(6) AND 
	NOT rdmult_cnt(7) AND NOT rdmult_cnt(8) AND NOT rdmult_cnt(9)));

FTCPE_rdmult_cnt13: FTCPE port map (rdmult_cnt(13),rdmult_cnt_T(13),exi_clk,'0','0');
rdmult_cnt_T(13) <= ((NOT exi_cs AND exi_in AND NOT exi_count(4) AND exi_count(3) AND 
	do_read AND inirdmult AND exi_count(2) AND NOT exi_count(1) AND 
	exi_count(0) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	NOT rdmult_cnt(13))
	OR (NOT exi_cs AND NOT exi_in AND NOT exi_count(4) AND exi_count(3) AND 
	do_read AND inirdmult AND exi_count(2) AND NOT exi_count(1) AND 
	exi_count(0) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	rdmult_cnt(13))
	OR (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(1) AND NOT exi_count(0) AND 
	NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND NOT rdmult_cnt(0) AND 
	NOT rdmult_cnt(10) AND NOT rdmult_cnt(11) AND NOT rdmult_cnt(12) AND NOT rdmult_cnt(1) AND 
	NOT rdmult_cnt(2) AND NOT rdmult_cnt(3) AND NOT rdmult_cnt(4) AND NOT rdmult_cnt(5) AND 
	NOT rdmult_cnt(6) AND NOT rdmult_cnt(7) AND NOT rdmult_cnt(8) AND NOT rdmult_cnt(9)));

FTCPE_rdmult_cnt14: FTCPE port map (rdmult_cnt(14),rdmult_cnt_T(14),exi_clk,'0','0');
rdmult_cnt_T(14) <= ((NOT exi_cs AND exi_in AND NOT exi_count(4) AND exi_count(3) AND 
	do_read AND inirdmult AND exi_count(2) AND exi_count(1) AND 
	NOT exi_count(0) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	NOT rdmult_cnt(14))
	OR (NOT exi_cs AND NOT exi_in AND NOT exi_count(4) AND exi_count(3) AND 
	do_read AND inirdmult AND exi_count(2) AND exi_count(1) AND 
	NOT exi_count(0) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	rdmult_cnt(14))
	OR (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(1) AND NOT exi_count(0) AND 
	NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND NOT rdmult_cnt(0) AND 
	NOT rdmult_cnt(10) AND NOT rdmult_cnt(11) AND NOT rdmult_cnt(12) AND NOT rdmult_cnt(13) AND 
	NOT rdmult_cnt(1) AND NOT rdmult_cnt(2) AND NOT rdmult_cnt(3) AND NOT rdmult_cnt(4) AND 
	NOT rdmult_cnt(5) AND NOT rdmult_cnt(6) AND NOT rdmult_cnt(7) AND NOT rdmult_cnt(8) AND 
	NOT rdmult_cnt(9)));

FTCPE_rdmult_cnt15: FTCPE port map (rdmult_cnt(15),rdmult_cnt_T(15),exi_clk,'0','0');
rdmult_cnt_T(15) <= ((NOT exi_cs AND exi_in AND NOT exi_count(4) AND exi_count(3) AND 
	do_read AND inirdmult AND exi_count(2) AND exi_count(1) AND 
	exi_count(0) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	NOT rdmult_cnt(15))
	OR (NOT exi_cs AND NOT exi_in AND NOT exi_count(4) AND exi_count(3) AND 
	do_read AND inirdmult AND exi_count(2) AND exi_count(1) AND 
	exi_count(0) AND NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND 
	rdmult_cnt(15))
	OR (NOT exi_cs AND NOT exi_count(4) AND NOT exi_count(3) AND 
	NOT inirdmult AND NOT exi_count(2) AND NOT exi_count(1) AND NOT exi_count(0) AND 
	NOT exi_count(5) AND NOT exi_count(6) AND NOT exi_count(7) AND NOT rdmult_cnt(0) AND 
	NOT rdmult_cnt(10) AND NOT rdmult_cnt(11) AND NOT rdmult_cnt(12) AND NOT rdmult_cnt(13) AND 
	NOT rdmult_cnt(14) AND NOT rdmult_cnt(1) AND NOT rdmult_cnt(2) AND NOT rdmult_cnt(3) AND 
	NOT rdmult_cnt(4) AND NOT rdmult_cnt(5) AND NOT rdmult_cnt(6) AND NOT rdmult_cnt(7) AND 
	NOT rdmult_cnt(8) AND NOT rdmult_cnt(9)));

Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC95144XL-5-TQ100


   --------------------------------------------------  
  /100 98  96  94  92  90  88  86  84  82  80  78  76  \
 |   99  97  95  93  91  89  87  85  83  81  79  77    |
 | 1                                               75  | 
 | 2                                               74  | 
 | 3                                               73  | 
 | 4                                               72  | 
 | 5                                               71  | 
 | 6                                               70  | 
 | 7                                               69  | 
 | 8                                               68  | 
 | 9                                               67  | 
 | 10                                              66  | 
 | 11                                              65  | 
 | 12                                              64  | 
 | 13               XC95144XL-5-TQ100              63  | 
 | 14                                              62  | 
 | 15                                              61  | 
 | 16                                              60  | 
 | 17                                              59  | 
 | 18                                              58  | 
 | 19                                              57  | 
 | 20                                              56  | 
 | 21                                              55  | 
 | 22                                              54  | 
 | 23                                              53  | 
 | 24                                              52  | 
 | 25                                              51  | 
 |   27  29  31  33  35  37  39  41  43  45  47  49    |
  \26  28  30  32  34  36  38  40  42  44  46  48  50  /
   --------------------------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 ide_adr<4>                       51 VCC                           
  2 KPR                              52 ide_dat<0>                    
  3 ide_adr<2>                       53 KPR                           
  4 KPR                              54 ide_dat<1>                    
  5 VCC                              55 KPR                           
  6 KPR                              56 ide_dat<2>                    
  7 KPR                              57 VCC                           
  8 KPR                              58 ide_dat<3>                    
  9 KPR                              59 ide_dat<4>                    
 10 KPR                              60 KPR                           
 11 KPR                              61 ide_dat<5>                    
 12 KPR                              62 GND                           
 13 ide_adr<1>                       63 KPR                           
 14 KPR                              64 ide_dat<6>                    
 15 ide_adr<0>                       65 KPR                           
 16 KPR                              66 ide_dat<7>                    
 17 KPR                              67 ide_dat<8>                    
 18 ide_adr<3>                       68 KPR                           
 19 KPR                              69 GND                           
 20 KPR                              70 ide_dat<9>                    
 21 GND                              71 KPR                           
 22 ide_rd                           72 ide_dat<10>                   
 23 ide_wr                           73 KPR                           
 24 KPR                              74 ide_dat<11>                   
 25 KPR                              75 GND                           
 26 VCC                              76 KPR                           
 27 KPR                              77 ide_dat<15>                   
 28 KPR                              78 ide_dat<14>                   
 29 KPR                              79 KPR                           
 30 KPR                              80 ide_dat<13>                   
 31 GND                              81 KPR                           
 32 KPR                              82 ide_dat<12>                   
 33 KPR                              83 TDO                           
 34 KPR                              84 GND                           
 35 KPR                              85 KPR                           
 36 KPR                              86 exi_clk                       
 37 KPR                              87 exi_in                        
 38 VCC                              88 VCC                           
 39 KPR                              89 KPR                           
 40 KPR                              90 exi_cs                        
 41 KPR                              91 KPR                           
 42 KPR                              92 exi_out                       
 43 KPR                              93 KPR                           
 44 GND                              94 KPR                           
 45 TDI                              95 KPR                           
 46 KPR                              96 KPR                           
 47 TMS                              97 KPR                           
 48 TCK                              98 VCC                           
 49 KPR                              99 KPR                           
 50 KPR                             100 GND                           


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         KPR  = Unused I/O with weak keeper (leave unconnected)
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc95144xl-5-TQ100
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Set I/O Pin Termination                     : KEEPER
Global Clock Optimization                   : OFF
Global Set/Reset Optimization               : OFF
Global Ouput Enable Optimization            : OFF
Input Limit                                 : 54
Pterm Limit                                 : 25