I don't know the part No. of the transmitter, of cause, in theory, it's just a LED, but I can't sure it has a resistor inside. if FPGA 3.3v IO direct connect to LED, it will burn LED or IO pin itself. LED is current driven device, not voltage driven. The SPDIF transmitter is not just a LED, it incl...

why do you need a transistor? the signal is connected to an optical transmitter...what is there that would cause any potential to drive the current over limits? within the optical connector the signal is tied to an LED....the LED is a diode...the optical receiver only receives optical data, it does...

I have since replaced all caps, resistors, and regs then tryed flashing the 0.2 update and 0.5 but no luck. One thing i did noticed is if i try to get a read back from the FPGA in impact it will fail. The SPI has been changed as well usually the bitsteam would load the FPGA config from SPI flash wh...

I have since replaced all caps, resistors, and regs then tryed flashing the 0.2 update and 0.5 but no luck. One thing i did noticed is if i try to get a read back from the FPGA in impact it will fail. The SPI has been changed as well usually the bitsteam would load the FPGA config from SPI flash wh...

@happy_bunny:

the tantalum-caps are all 20V 1uF,
ucf change: TIMESPEC TS_CLOCK_54 = PERIOD "CLOCK_54" 70 MHz HIGH 50 %;

and the last,
the buffering in the gcdv_decode.vhd is hardly fit into the FPGA, so I can't keep them.

well, here is the video:

http://player.youku.com/player.php/sid/ ... Mg==/v.swf

Can you explain more dont understand is 0.5 also bad on your setup. Oh, I fixed the problem, first is edit ucf file under planahead, give TS_CLOCK_54 more strict constraint, for example, 70Mhz, this give me more stable synthesize result. then I measure the 1.2v LDO input and output using oscillsoco...

due to timing analysis, maximum frequency of 0.2 version can reach to 83.6 Mhz, but 0.5 is only 54.2 Mhz, I think 54.2 Mhz is a critical condition for stable

megalomaniac wrote:@HyperIris
with 0.4 or even 0.3 do you notice any elevated temperature of the chip?
if so, can you remove the spdif port and try the tests again to check thermal increase of the chip...

no, I'm not connected the SPDIF port, the FPGA chip is cold (as room temperature).

Oh... 0.4 version still very unstable...

look this, unstable video with noisy audio:

http://v.youku.com/v_show/id_XMTMyNjk3N ... s1.8-1-1.2

@HyperIris I think its noise with only the video stuff only ond DCM block was used running at 54Mhz with audio you have two clock circuits running. I think the ground plane is jumping / noisy due to the clocks can you try this please (dam it didnt let me attach the vhdl) its from gcdv_decoder.vhd T...

@hyperIris will do a diff between the 0.2 and 0.3 tonight and see what I did. Cant remember the differences now, maybe I can spot something wrong. I've done diff between the 0.2 and 0.3 source, I think there is NOT ANY wrong in your modification. the only different is audio part. So I really can't ...

I have enough FPGAs and PCBs for build other 8 boards, so this is not a problem.

Oh thats a bit weird does version 0.3 work on your tv 0.3 half works, it has some green noise pixels on screen, here are some photos taken from my TV: http://ww2.sinaimg.cn/mw1024/755c416fgw1evp2vgzgkoj21kw16oqjc.jpg http://ww4.sinaimg.cn/mw1024/755c416fgw1evp2vn6n7kj21kw16odwo.jpg http://ww3.sinai...

@happy_bunny, I've tested your new firmware, but I can't get any video/audio output on my TV, it's not hardware fail because when I flash the old firmware (0.2 version), it works again.

WHAT A GREAT NEWS FOR US!

thank you!

Crazynation‘s design is just a prototype like one.

I've make up another one like this: viewtopic.php?f=31&t=184&p=1137#p1137

AFAIK, the audio from GC's Digitial port is some kind of "I2S like" data stream, so I think merge it into the GCVideoLite(Shuriken Video) is possible. (I'm not familiar with DVI/HDMI spec so I can't work at this issue) here is a HDMI Audio project for reference: https://gitlab.com/lantti/...

AFAIK, the audio from GC's Digitial port is some kind of "I2S like" data stream, so I think merge it into the GCVideoLite(Shuriken Video) is possible. (I'm not familiar with DVI/HDMI spec so I can't work at this issue) here is a HDMI Audio project for reference: https://gitlab.com/lantti/h...

R7 is 180 ohm. And if you can download to FPGA, I guess that you have xilinx platform cable usb or other JTAG cable, so JP1 is not necessery. Just init JTAG chain under xilinx iMpact, and Program SPI flash via JTAG chain. It will cost you 5~~10 seconds. Program SPI Flash is enough, download to FPGA ...

@ HyperIris nice work :D very cool by my test, I have many GCs, include NTSC-u/j and PAL, they all works. more pics and bottom half of 3d case on my webpage. Cool thank you, I'm only missing some little caps and resistors. Can you put the corresponding number on the board ( like U2 and U4 ) to the ...

BTW, the SPI flash 25P40 is much larger for xc3s50A.
IMO, may be 25P10 is enough (cheaper?).

the only parts that don't have product numbuer are the two LDOs, the 5V one is 1117-5.0 and 1.2V is MCP1826s-12. see posts in page 4.

so I don't think "no BOM file in happy_bunny's files", reference the schemtic for all other parts.

Pal or ntsc-u/j? And very good job by my test, I have many GCs, include NTSC-u/j and PAL, they all works. on my TV, the TV says NTSC-u/j display 480i, and PAL display 576i under interlaced scanning mode, and all shows 480p input signal under progressive mode. We ntsc-u users are having problems wit...

andre104623 wrote: Pal or ntsc-u/j? And very good job

by my test, I have many GCs, include NTSC-u/j and PAL, they all works.

on my TV, the TV says NTSC-u/j display 480i, and PAL display 576i under interlaced scanning mode, and all shows 480p input signal under progressive mode.