Just a "quick" chime-in to say that the basic GC Digital AV code is working on the FPGA.
No HDMI output yet, as it needs to be modified to work with the GC's interlaced output.
I'm just sorting out a modchip for this PAL GC too, so I can use progressive mode via HDMI.
Basically it's running from the Digital AV output via the FPGA then out to VGA on my dev board.
(It's using some sigma-delta DAC code for the VGA testing, so it's a bit fuzzy atm, understandably).
It is also outputting YPrPb (component style) colour, but my old Pioneer plasma can switch to component colour space so I can see it properly.
The Pioneer also supports interlaced via the VGA socket, which is a bit hit-and-miss these days. lol
It will need a YCrCb to RGB code block for proper RGB / VGA output, but the image is perfectly stable (apart from the above mentioned fuzzy stuff).
So, we now know the Digital Vid interface isn't so mysterious after all.
Sorry, no photos just yet, need some sleep first (it's 5am here now), but here's the first SigTap capture...
http://i40.tinypic.com/2ynq63q.jpg
And here's a better one with the flags / sync stuff added...
http://i39.tinypic.com/33ehc1k.jpg
btw, on the gamesx pinout, the "ClkSelect" signal is actually called "vphase" or "VICR" in the GC patent.
When this signal is HIGH, you grab the Cr byte after Y.
When it's LOW, you grab the Cb byte after Y.
As described in the patent / gamesx; when the "Y" byte equals 0x00 (right after "vphase" toggles), the Cr / Cb bytes then denote the "flag" bytes.
You can then extract the various sync / flag bits...
Code: Select all
gc_inter_n <= vdata[0]; // I
gc_pal <= vdata[1]; // M
gc_burst_blank <= vdata[2]; // K
gc_burst <= vdata[3]; // B
gc_hsync_n <= vdata[4]; // H
gc_vsync_n <= vdata[5]; // V
gc_field <= vdata[6]; // F
gc_csync_n <= vdata[7]; // C
A "gc_blank" flag can be set when Y == 0x00 as well.
The 54MHz and 27MHz clock outputs from the GC are normally free-running, so it's the just actual pixel rate which changes to 54MHz for prog mode (dependant on the software, as mega dude reminded me.).
The above captures were with interlaced mode ofc, so this is a 27MHz pixel rate (that "DVI_PLL" signal is 27MHz).
EDIT: Technically, the "pixel" rate in interlaced mode is only 13.5MHz as you'd expect, 'cos there's only one "Y" (luminance) byte for every two 27MHz clocks.
Each of the colour difference signals is only half the sampling rate (6.25MHz) of the luminance . This is a VERY common SD video sampling standard.
Early days yet, but thought I'd leave an update if anyone's interested?
Can't promise a that finished product will definitely, but I'm hoping this will at least lead to something nice.
(Might work on non-Dig AV GC's as well, but soldering to the DAC won't be easy.)
OzOnE.
