gc-forever - Gamecube/Wii Forums

Bus interface features include the following
– Selectable bus-to-core clock frequency ratios of 2x, 2.5x, 3x, 3.5x, 4x, 4.5x ... 8x and 10x. (2x to 8x, all half-clock multipliers in-between)
– A 64-bit, split-transaction external data bus with burst transfers
– Support for address pipelining and limited out-of-order bus transactions
– Single-entry load queue
– Single-entry instruction fetch queue
– Two-entry L1 cache castout queue
– No-DRTRY mode eliminates the DRTRY signal from the qualified bus grant. This allows the forwarding of data during load operations to the internal core one bus cycle sooner than if the use of DRTRY is enabled.

1.2.9 Clocking
Gekko requires a single system clock input, SYSCLK, that represents the bus interface frequency. Internally, the processor uses a phase-locked loop (PLL) circuit to generate a master core clock that is frequency-multiplied and phase-locked to the SYSCLK input. This core frequency is used to operate the internal circuitry.
The PLL is configured by the PLL_CFG[0–3] signals, which select the multiplier that the PLL uses to multiply the SYSCLK frequency up to the internal core frequency. The feedback in the PLL guarantees that the processor clock is phase locked to the bus clock, regardless of process variations, temperature changes, or parasitic capacitances.
The PLL also ensures a 50% duty cycle for the processor clock.
Gekko supports various processor-to-bus clock frequency ratios, although not all ratios are available for all frequencies. Configuration of the processor/bus clock ratios is displayed through a Gekko-specific register, HID1. For information about supported clock frequencies, see the Gekko hardware specifications.