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CPU Xilinx XC95144XL
GC Interface Memory Card Slot A/B
HDD Interface IDE Hard Disk Drive
Max Supported 128PB
SATA IC (M.2 Loader only) JMicron JM20330
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General information

The IDE-EXI originated from a design by by Dampro (Damián), where he wanted to use whatever electronics he had lying around to get his GC to boot backups via modifying SD-Boot. His initial design/spec/code/tutorial is located here and is intended for those who already have some device (PS2 Xilinx based modchip) for parts. The code was re-used in a redesigned version intended for the memory card slot with the help of bushing from Team Twiizers designing the PCB - this is what everyone has known as the IDE-EXI.

Gamecube with IDE-EXI connected
Gamecube with IDE-EXI connected in Slot B


The IDE-EXI has its own dedicated sub forum.

IDE-EXI Availability

There was a batch of 100 IDE-EXI's produced and sold at GC-Forever, they sold within a day or two. A few months after, the files to have your own (mass) produced were released. Badassconsoles produced a second batch at some point which were released to the public. No more have been produced to this date on a large scale, however users can always build their own all that is required is the Xilinx and time :)

IDE-EXI back showing credits
IDE-EXI back showing credits

M.2 Loader

webhdx released a variant of the IDE-EXI with a in-built SATA to IDE IC (with a M.2 connector) for Serial Port 1. This is based on the version 2 DMA fixed source code and has support integrated into Swiss itself now.

IDE-EXI limitations

The Gamecube EXI bus has a bug in which every time data goes across the input line, the same data is written back out shifted right by 1. Due to this, the initial code cannot have DMA transfers performed, which limits speed (not 100% confirmed at this point). isobel from has fixed this bug, however this is in testing at the moment.

DMA Support was tested but what occurs is that if you DMA more than 1 sector of data over, the GameCube will DMA read too fast for the HDD to have prepared the data for the second sector. This causes random garbage bytes to appear mid DMA stream. More testing at slower speeds is required and single sector DMA too.