http://www.ebay.co.uk/itm/Altera-Cyclon ... 25754d6042
(can't find my exact board atm?)
The design is fairly small though, and even with the SDRAM scan doubler it only needs around 45% of the EP2C8.
I still have the "new" US GC sitting here, and I've already installed the first Xeno chip into the PAL one, but I just have SO many other projects on the go at the same time.
I'm intending to work on this again soon, but need to sort out these other projects first (such as the DC IDE adapter).
I think the YCbCr stream is very close to the bt.601 / bt.656.
Well, I suppose the timings for interlaced modes are basically the same, it just needs the SAV / EAV flags to be injected?
As for the code itself, I simply used the info on gamesx and the GC patent to extract the YCbCr and "Flags" bytes.
The info in this post gives quite a lot to go on, but please let me know if you need further info...
viewtopic.php?p=18052#p18052
And here's the patent (pages 21 and 22 for the vid protocol)...
http://www.google.com/patents?id=Rk0NAA ... &q&f=false
I can't really post the full code atm, but don't mind giving help / suggestions.

The protocol simply gives the vert / horiz / blanking / burst signals directly, but the DAC itself must be adding the actual colour bursts.
I only know Verilog tbh (and still learning at that).
I can mostly read VHDL, but it's very ugly / verbose and I've never quite understood it's appeal.
If I find a chunk of VHDL I want to understand, I generally convert it to Verilog first (with X-HDL or Veritak).
OzOnE.