Shuriken Video

[HyperIris]

due to timing analysis, maximum frequency of 0.2 version can reach to 83.6 Mhz, but 0.5 is only 54.2 Mhz, I think 54.2 Mhz is a critical condition for stable

[happy_bunny]

Can you explain more dont understand is 0.5 also bad on your setup.

[HyperIris]

Can you explain more dont understand is 0.5 also bad on your setup.

Oh, I fixed the problem, first is edit ucf file under planahead, give TS_CLOCK_54 more strict constraint, for example, 70Mhz, this give me more stable synthesize result.

then I measure the 1.2v LDO input and output using oscillsocope, I find that thay are noisy, so I add three tantalum-caps, look like this:





now 0.5 version works very nice.

[HyperIris]

well, here is the video:

http://player.youku.com/player.php/sid/ ... Mg==/v.swf

[happy_bunny]

thank you for looking into this for me you are a star

which value did you use for the tantalum-caps ? can you copy paste (upload) the ucf changes please. Also did you keep the buffering in the gcdv_decode.vhd file ?

thanks again dude

[HyperIris]

@happy_bunny:

the tantalum-caps are all 20V 1uF,
ucf change: TIMESPEC TS_CLOCK_54 = PERIOD "CLOCK_54" 70 MHz HIGH 50 %;

and the last,
the buffering in the gcdv_decode.vhd is hardly fit into the FPGA, so I can't keep them.

[happy_bunny]

"The 1.2 vreg is the same as the pluto board but the input and ouput caps are different maybe they need to be beefed up."

This is incorrect I have had time to check and the pluto board uses a AMS1117 (well the one I have does)

http://www.advanced-monolithic.com/pdf/ds1117.pdf

This has a max current output of 1.5A, currently on the board I created it has a MCP1826

http://www.farnell.com/datasheets/1769092.pdf

This has a max current output of 1A.

@HyperIris

Datasheet states 4.7uF input cap and 1uF output cap, so I would suggest changing the input cap to 4.7uF.

@andre104623 and any else with a SPDIF connector.

I think filling up the fgpa made my board draw double the current and then on top of that connecting the SPDIF connector resulted in the 1.2reg dropping below 1.2volts which I think then caused the fpga to run hot hopefully the 1.2vreg gave up in the end before the fpga got damaged.

I would recommend disconnecting SPDIF connect or upgrading your 1.2 vreg for this one MCP1827 (farnell no 1852008) 1.5A

http://www.farnell.com/datasheets/456104.pdf

Also upgrade the input / output caps to 4.7uF and 1uF that will help make your vreg stable at the higher currents, will update my website later with this info.

[andre104623]

I have since replaced all caps, resistors, and regs then tryed flashing the 0.2 update and 0.5 but no luck. One thing i did noticed is if i try to get a read back from the FPGA in impact it will fail. The SPI has been changed as well usually the bitsteam would load the FPGA config from SPI flash which is fine I can flash the SPI but if the read back is failing i would guess the FPGA is fried. Maybe it was the SPDIF or the TV i was using back feeding 5v then that could of done it I'm not really sure but the SPDIF was powered by the power rail of the cube so i really dont think that was the reason

[HyperIris]

I have since replaced all caps, resistors, and regs then tryed flashing the 0.2 update and 0.5 but no luck. One thing i did noticed is if i try to get a read back from the FPGA in impact it will fail. The SPI has been changed as well usually the bitsteam would load the FPGA config from SPI flash which is fine I can flash the SPI but if the read back is failing i would guess the FPGA is fried. Maybe it was the SPDIF or the TV i was using back feeding 5v then that could of done it I'm not really sure but the SPDIF was powered by the power rail of the cube so i really dont think that was the reason

you mean that you connected the FPGA spdif pin DIRECT to something like 5V TTL cricuit without any protect?

[andre104623]

I have since replaced all caps, resistors, and regs then tryed flashing the 0.2 update and 0.5 but no luck. One thing i did noticed is if i try to get a read back from the FPGA in impact it will fail. The SPI has been changed as well usually the bitsteam would load the FPGA config from SPI flash which is fine I can flash the SPI but if the read back is failing i would guess the FPGA is fried. Maybe it was the SPDIF or the TV i was using back feeding 5v then that could of done it I'm not really sure but the SPDIF was powered by the power rail of the cube so i really dont think that was the reason

you mean that you connected the FPGA spdif pin DIRECT to something like 5V TTL cricuit without any protect?

No i used a 3.3 volt lite-on optical transmitter same one approved for the pluto 2x hdmi

[HyperIris]

I have since replaced all caps, resistors, and regs then tryed flashing the 0.2 update and 0.5 but no luck. One thing i did noticed is if i try to get a read back from the FPGA in impact it will fail. The SPI has been changed as well usually the bitsteam would load the FPGA config from SPI flash which is fine I can flash the SPI but if the read back is failing i would guess the FPGA is fried. Maybe it was the SPDIF or the TV i was using back feeding 5v then that could of done it I'm not really sure but the SPDIF was powered by the power rail of the cube so i really dont think that was the reason

you mean that you connected the FPGA spdif pin DIRECT to something like 5V TTL cricuit without any protect?

No i used a 3.3 volt lite-on optical transmitter same one approved for the pluto 2x hdmi

do you append a driver transistor to drive the transmitter? I guess that use FPGA drive transmitter directly will makes FPGA over current and burned.

[megalomaniac]

why do you need a transistor?
the signal is connected to an optical transmitter...what is there that would cause any potential to drive the current over limits?

within the optical connector the signal is tied to an LED....the LED is a diode...the optical receiver only receives optical data, it does not transmit...the optical transmitter is powered by 3v source for the LED...
this basic design and functionality allows the FPGA and any other equipment to be electrically isolated from other components (aka audio system)

[HyperIris]

why do you need a transistor?
the signal is connected to an optical transmitter...what is there that would cause any potential to drive the current over limits?

within the optical connector the signal is tied to an LED....the LED is a diode...the optical receiver only receives optical data, it does not transmit...the optical transmitter is powered by 3v source for the LED...
this basic design and functionality allows the FPGA and any other equipment to be electrically isolated from other components (aka audio system)

I don't know the part No. of the transmitter, of cause, in theory, it's just a LED, but I can't sure it has a resistor inside. if FPGA 3.3v IO direct connect to LED, it will burn LED or IO pin itself.

LED is current driven device, not voltage driven.

[Unseen]

I don't know the part No. of the transmitter, of cause, in theory, it's just a LED, but I can't sure it has a resistor inside. if FPGA 3.3v IO direct connect to LED, it will burn LED or IO pin itself.

LED is current driven device, not voltage driven.

The SPDIF transmitter is not just a LED, it includes a driver circuit and the input is a TTL-compatible logic signal. See the datasheet here.

[HyperIris]

I don't know the part No. of the transmitter, of cause, in theory, it's just a LED, but I can't sure it has a resistor inside. if FPGA 3.3v IO direct connect to LED, it will burn LED or IO pin itself.

LED is current driven device, not voltage driven.

The SPDIF transmitter is not just a LED, it includes a driver circuit and the input is a TTL-compatible logic signal. See the datasheet here.

got, that, so this type of transmitter is safe for use.

[happy_bunny]

oh Current Consumption IDD of only 8mA, and its being driven of the cubes supply rail this is a puzzle very odd. So it works running cool with 0.2 without the SPDIF connected. Then you upgraded to 0.3 and it got hot, at anytime did you run 0.3 without the SPDIF connected with 0.3 ? Did it get hot? just wondering if the SPDIF pin coming out from the FPGA was somehow shorting to ground, you did get audio out of the SPDIF didnt you ? so it cant have been fully shorted.

If the pins on a FPGA are not used they go tri-state right ? or are they ties to ground? is it one of the options in the project settings? I am thinking maybe the pin was always slightly shorted but it was not notices as that pin was tri-state. An upgrade to 0.3 would have started driving that pin, IF and this is a big IF it was somehow shorted to ground that would make the FPGA get warm.

[Unseen]

is it one of the options in the project settings?

It's a setting in the bit stream generation. I think the default is "Pullup".

[andre104623]

I think mega could be right in saying that the hotel TV I was the reason that my shuriken video died because I didn't have any issues with it at home before I left. It's not a big deal total cost in parts and bare PCB's comes to 30 about so no biggie I could just build one more but there are bigger things around the corner like mega's GCvideo which I might buy and put in the same cube. I like the OSD settings makes the DVI version really unique so I'm not sure what I might do yet. My wasp fusion cube has the pluto board installed so I been using that

[happy_bunny]

ordered v3 boards managed to cut 10mm of the length not as much as I wanted, will see how it fits into the cube hopefully no hacking of the case this time round.

video_v3.png

(110.38 KiB) Not downloaded yet

[andre104623]

ordered v3 boards managed to cut 10mm of the length not as much as I wanted, will see how it fits into the cube hopefully no hacking of the case this time round.

video_v3.png

God, I do think it was already small but if you would just put the HDMI at a right angle you could save space and not have exposed PCB out the back of the cube. I think V2 is perfect size for it's design but if you want nothing there look then right angle HDMI could be your answer.

[TALANTO]

Thank you for sharing these awesome projects!

happy_bunny,
I am interested in flashing the board with your program "fpga_flash.exe" via parallel port and I couldn't find anyone to ask about it. I have got an old PC with parallel port and I have finally found few schematics. Would you tell me is this the right way to program the board, thanks.

Spoiler

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[happy_bunny]

if you want to flash the chips before you put them on the pcb you will need something like this

program_flash_without_power.jpg

(418.38 KiB) Not downloaded yet

however if you are programming them after they have been placed on the pcb you dont need to supply power

program_flash_on_pcb.jpg

(420.11 KiB) Not downloaded yet

nice to meet someone that still has a parallel port although my old pc is almost dead video cards starting to die.

[TALANTO]

Thank you again.

I think there is a cheap solution for people without parallel ports. They can buy cheap programmer (CH341A) which can write "spi_flash.bin" to M25P40, after that build the board and test. Will this work or I am missing something?

[marcus9199]

Finally got mine going! Man I have to say the hardest part was trying to program it on win 10. I had to substitute the 4.7 uf cap for a through hole one. I didn't see a voltage rating in the schematic. But apparently 10v was not enough I kept smoking them. This is a 35v.

[happy_bunny]

@TALANTO

may buy that cheap programmer see if it works

@marcus9199

you sure you had the input cap the right way round, 10V should have been enough having said that I think the ones I have are 16 volt.

got the v3 boards today have not got a clue if they work need to check at the weekend but heres a pic

20151119_211940.jpg

(1.96 MiB) Not downloaded yet